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deep submicron vlsi technology and research papers



Accurate thermal noise model for deep-submicron CMOS
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Abstract Extensive measurements of drain current thermal noise are presented for 3 different CMOS technologies and for gate lengths ranging from Zum down to 0.17 um. Using a surface-potential-based compact MOS model with improved descriptions of carrier ABSTRACT The increased background leakage current of deep submicron devices threatens the practical application of the traditional

Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors
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Abstract This paper presents new insights into the mechanisms of gate depletion and boron penetration in deep submicron CMOS technologies. MOSFET matching measurements show that these effects are stochastic in nature, and are associated with the gate poly-Si

Conquering noise in deep-submicron digital ICs
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ABSTRACT Design methodologies for digital integrated circuits are ultimately concerned with validating a design against metrics which ensure functionality, testability, and that the design satisfies power and timing requirements. Electronic design automation (EDA) tools

An integrated environment for technology closure of deep-submicron IC designs
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ABSTRACT p With larger chip images and increasingly aggressive technologies, key design processes must interoperate. PDS, a physical-synthesis system, accomplishes technology closure through interacting processes of logic optimization, placement, timing,

The APV25 deep submicron readont chip for CMS detectors
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Abstract The APV25 is a 128 channel analogue pipeline chip for readout of silicon microstrip detectors in the CMS tracker at the LHC. Each channel comprises a low noise amplifier, a 192 cell analogue pipeline and a deconvolution readout circuit. Output data are

Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies
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Abstract Parametric mismatch and fluctuations can affect the performance of deep- submicron digital and mixed-signal CMOS processes in many ways. It is shown that microscopic stochastic device property fluctuations like dopant fluctuations form a serious

RF-distortion in deep-submicron CMOS technologies
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Abstract The distortion behaviour of MOSFETs is important for RF-applications. In this paper the inuence of technology varia-tions (oxide thickness, substrate doping,) on distortion is. investigated using measurements and a recently developed compact MOSFET model. This tutorial will focus on (1) the new validation and test issues,(2) basic models and analysis of the related underlying electrical phenomena,(3) techniques to generate tests for validation and testing, which would take into account these issues, and (4) several real-life

Device parameter changes caused by manufacturing fluctuations of deep submicronMOSFET's
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Abstract-The effects of typical manufacturing fluctuations upon four electrical device parameters: threshold voltage, transconductance, substrate current and off current have been studied for deep submicron MOSFET's (0.1 pm). The analysis reveals that the

Effective power and ground distribution scheme for deep submicron high speed VLSI circuits
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ABSTRACT This paper studies the power and ground distribution and its noise effect for deep submicron CMOS VLSI circuits. It is found that orders of magnitude reduction in switching noise can be achieved using an effective power and ground distribution scheme

The EKV 3.0 compact MOS transistor model: accounting for deep-submicron aspects
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ABSTRACT The EKV 3.0 compact MOS transistor model for advanced IC design is presented. Its basis is an ideal analytical charge-based model including static to non- quasistatic dynamic aspects and noise. The ideal model is extended to account for the

Continuing experiments of atmospheric neutron effects on deep submicron integrated circuits
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Just as the Rosetta Stone enabled researchers to decode the unsolvable and mysterious Egyptian hieroglyphs by comparing them to the same text written in a known language, the Xilinx Rosetta experiments link two prior known and well-documented techniques of

Development of a radiation tolerant 2.0 V standard cell library using a commercial deep submicron CMOS technology for the LHC experiments
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Abstract A standard cell library was developed using a commercial 0.24 µm, 2.5 V CMOS technology. Radiation tolerant design techniques have been employed on the layout of the cells to achieve the total dose hardness levels required by LHC experiments. The library ABSTRACT Today's built-in current sensor (BICS) techniques provide I/sub DDQ/current sensitivity which is adequate for testing and diagnosing near-micron CMOS ICs. However, faulty and fault-free I/sub DDQ/can become indiscernible at deep submicron levels. This

RF-noise of deep-submicron MOSFETS: Extraction and modeling
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Abstract A method for the extraction of all four noise parameters of a MOSFET (channel noise, induced gate noise and complex correlation coefficient) based on a description of noise by means of correlation matrices is presented. For the first time values for the gate

FW Modeling Issues. of Deep-submicron MOSFETs for Circuit Design
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Abstract in deep submicron transistors with transit frequencies in This issues in CMOS MOSFET modeling for radio frequency performance is attractive for HF circuit design in view (RF) applications. Beginning with a brief review of of a system-on-a-chip realization,

Current-based testing for deep-submicron VLSIs
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ABSTRACT Current-based testing for deep-submicron VLSIs is important because of transistor sensitivity to defects as technology scales. However, unabated increases in leakage current in CMOS devices can make this testing very difficult. This article offers

The effect of logic block granularity on deep-submicron FPGA performance and density
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Page 1. THE EFFECT OF LOGIC BLOCK GRANULARITY ON DEEP-SUBMICRON FPGA PERFORMANCE AND DENSITY by ii Page 3. Abstract The Effect of Logic Block Granularity on Deep-Submicron FPGA Performance and Density Elias Ahmed Master of Applied Science ABSTRACT p Very deep-submicron technologies pose new challenges to IC testing. In particular, crosstalk and transient faults are difficult to detect with traditional methods. Online testing techniques can detect these faults, however, and a new approach extends these

Requirements for practical I DDQ testing of deep submicron circuits
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ABSTRACT This paper describes the requirements that quiescent current (I sub DDQ /sub ) testing must meet in order to continue being useful in the face of rising background currents. Using projections from the 1999 International Technology Roadmap

Reliable circuit techniques for low-voltage analog design in deep submicron standard CMOS: A tutorial
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We present in this paper an overview of circuit techniques dedicated to design reliable low- voltage (1-V and below) analog functions in deep submicron standard CMOS processes. The challenges of designing such low-voltage and reliable analog building blocks are

BIST for deep submicron asic memories with high performance application
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ABSTRACT Today's ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tight layouts. These two trends are putting much greater demands upon

Characterizing substrate coupling in deep-submicron designs
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ABSTRACT p The accurate modeling of noise-coupling effects caused by crosstalk through the substrate is an increasingly important concern for design and verification of analog, digital, and mixed systems. With the technique described here, designers can

Deep submicron bus invert coding
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ABSTRACT In this paper we present a simplified model for deep submicron, on-chip, parallel data buses. Using this model a coding technique similar to Bus Invert Coding is presented, but with a better performance in the proposed model. The coding technique

Analyzing sigma-delta ADCs in deep-submicron CMOS technologies
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Sigma-delta (S) analog-to-digital-converters are critical components in wireless transceivers. This study shows that a continuous-time, single-loop, single-bit S ADC is suitable for wireless applications demanding less than 5 MHz conversion bandwidth (

Deep-submicron CMOS warms up to high-speed logic
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L. Mmzriing/We. r/light ilicon bipolar de\ ices. purticulztrly those in emitterecoupled logic (ECL). have been accepted as the most useful of the various high-speed technologies since [Cs were rst introduced into computers. But the possibilities for improving F. CL will even

High-performance pipeline A/D converter design in deep-submicron CMOS
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The rapid evolution of the silicon integrated circuits (IC) during the last two decades has enabled the miniaturization of narrow-band mobile phones that can operate on batteries for reasonable lifetimes. The aggregation of the research results of the radio-frequency (RF)

Modeling the effect of wire resistance in deep submicron coupled interconnects for accurate crosstalk based net sorting
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Abstract: It is well known that in deep submicron technologies the coupling capacitance between adjacent wires is a critical portion of the total wire capacitance, while at the same time the capacitance between wire and substrate has become the fringing component.

Extended charges modeling for deep submicron CMOS
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Abstract-The simulation of deep submicron CMOS cir-cuits operating at high-frequency requires adequate models representing the dynamic behavior of the transistors. Charges in the device are affected by carrier quantization and polydepletion in the gate. Velocity

High-reliability deep submicron GaAs pseudomorphic HEMT MMIC amplifiers
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Abstract High-reliability performance of a Q-band MMIC amplifier fabricated using TRW's 0.1 µm production AlGaAs/GaAs HEMT process technology is reported. Operating at an accelerated life test conditions of Vds= 4.2 V and Ids= 150mA/mm, two-stage balanced

Analog design in deep submicron CMOS processes for LHC
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Abstract The feasibility of analog integrated circuits for LHC experiments in deep submicron CMOS technologies has been investigated. This paper discusses general design issues and presents a systematic study of fundamental analog characteristics of commercial deep

Dynamic circuit techniques in deep submicron technologies: Domino logic reconsidered
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ABSTRACT Dynamic circuit techniques offer potential advantages over static CMOS. Domino circuits are the most widespread representative in high performance designs but suffer increasingly from deep submicron effects. This paper presents evaluations in terms

Measurement and characterization of multi-layered interconnect capacitance for deep submicron VLSI technology
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V91 Proc. IEEE 1997 Int. Conference on Microelectronic Test Structures, Vol 10, March 1997. Measurement and Characterization of Multi-Layered Interconnect Capacitance for Deep Submicron VLSI Technology Dae-Hyung Cho, Man Ho Seung, Nam-Ho Kim, and

VHDL-AMS design of a MOST model including deep submicron and thermal-electronic effects
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Abstract The paper presents an application of the VHDL-AMS formalism to the model of a n- MOS transistor named EKV. Our model takes into account several new features specific to deep submicron technology (parasitic resistors and overlap capacitors induced by LDD),

Gate polysilicon optimization for deep-submicron MOSFETs
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Abstract The use of amorphously deposited silicon and fine-grained polysilicon as MOS gate material is discussed. A variety of deposition and anneal conditions was evaluated on MOS capacitors and transistors. Gate depletion and MOSFET matching have been studied as a

Inversion layer quantization impact on the interpretation of 1/f noise in deep submicronCMOS transistors
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basis of BSIM and other equivalent engineering models. Another consequence is that we may be probing different types of traps in deepsubmicron technologies at high V G compared with previous CMOS generations. Page 12. imec 2002 ESSDERC 2002/ Firenze/ ES 12

Deep-submicron structures in YBCO: fabrication and measurements
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Abstract-We present a fabrication method that consis-tently produces superconducting stroctures with lateral dimensions down to 100 nm. The etching is done in a Distributed Electron Cyclotron (ECR-) etcher using a plasma of argon and oxygen. The sample is ABSTRACT In this paper, we review the algorithms and methodologies used for interconnect analysis in deep submicron integrated circuits. In particular, we examine the techniques that have been practically used for static timing and static noise analysis in the design of high-

Asymmetric-cell caches: Exploiting bit value biases to reduce leakage power in deep-submicron, high-performance caches
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Abstract We propose a novel approach that leverages circuit-and architecture-level techniques to drastically reduce leakage power dissipation in high-performance caches even when most of the cache cells are actively used. We observe that the cache resident

A high compliance input and output regulated body-driven current mirror for deep-submicron CMOS
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I. INTRODUCTION he current mirror (CM) remains a critical building block of analog VLSI circuits. In accordance with Moores Law, MOSFET feature sizes continue to be reduced, which in turn increase the difficulties in designing highYperformance analog circuits in

Hydrodynamic simulation of RF noise in deep-submicron MOSFETs
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Abstract:A noise model for MOSFETs based on analytical microscopic noise sources has been developed and noise simulations based on the hydrodynamic model have been performed. The drain and gate excess noise parameters and correlation coefficient are

Mixed analog-digital design considerations in deep submicron CMOS technologies
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Abstract Higher speed and higher density are the main thrusts of CMOS technology and are achieved by device miniaturization. In deep submicron geometries, the supply voltage is scaled down to prevent reliability hazards such as oxide breakdown and hot carrier effects

Reduction of band-to-band tunneling in deep-submicron CMOS single photon avalanche photodiodes
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SUMMARY We demonstrate that a process layer intended for pinnedphotodiode formation can be employed to reduce the dark count rate (DCR) of single photon avalanche diodes (SPADs) in nanometer-era CMOS technologies. A low-doped p-type passivation implant

P7: A Vertically Integrated High Resolution Active Pixel Image Sensor for Deep SubmicronCMOS Processes
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Abstract A novel high resolution active pixel sensor in TFA technology has been fabricated. TFA technology [1] employs an amorphous silicon (a-Si: H) based thin film detector on top of an ASIC. The two components can be optimized independently of each other, and fill

A simple model for digital/analog crosstalk simulation in deep submicron CMOS technology
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Abstract:This paper illustrates a simple model of digital/analog crosstalk, suitable for simulation of digital switching noise in integrated circuits with highly doped substrate and epitaxial layer. The proposed model is suitable for analog simulations using any SPICE-

A technology-based compact model for predictive deep-submicron MOSFET modeling and characterization
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ABSTRACT This paper presents new development results of our compact model (Xsim) for deep-submicron MOSFETs. Although a threshold-voltage-based and source-referenced regional model, Xsim meets the basic requirements of continuity (to third-order derivatives

Challenges for SoC Design in Very Deep Submicron Technologies
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Page 1. 1 Challenges for SoC Design in Very DeepSubmicron Technologies James Lin Vice President, Technology Infrastructure Group National Semiconductor Corporation CODES + ISSS 2003 October 3rd, 2003 Page 2. 2 2003 National Semiconductor Corporation

Test and debug in deep-submicron technologies
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Abstract With the scaling of feature sizes into Deep-Submicron (DSM) values, the level of integration and performance achievable in VLSI chips increases. A lot of work has been directed to tackle design related issues arising out of scaling, like leakage mitigation etc.

ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure
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Abstract A novel ESD protection circuit, which first combines the advantages of complementary low-voltage-trigger SCR devices and the gate-couple technique, is proposed to more effectively protect the thinner gate oxide of deep submicron CMOS IC's

New process technology for CD control in deep-submicron optical lithography
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An effective and practical control technology of critical dimensions for submicron VSLI is presented. An ARCOR (Anti-Reflective Coating On Resist) process was improved, which is applied as a transparent type anti-reflective coating. A water soluble and low refractive

AC and noise analysis of deep-submicron MOSFETs
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ABSTRACT The AC and noise simulation of deep-submicron MOS device has emerged as a very important issue as device size scales down and the operational frequency of CMOS circuit rises. However, the quantum mechanical effects and high energy carriers in deep-

On the origin of the 1/f1. 7noise in deep submicron partially depleted SOI transistors
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Abstract Results are presented of a systematic low-frequency (LF) noise study of deep submicron transistors processed in a 0.1 µm partially depleted (PD) Silicon-on-Insulator (SOI) technology. The focus is on a particular kind of noise, which is termed 1/f1. 7 noise,

Impact ionization process in deep submicron MOSFET
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Abstract:Within the framework of Keldysh impact ionization model the calculation of effective threshold energy for silicon MOSFET with 100 nm channel length by means of ensemble Monte-Carlo simulation is performed. The possibility of impact ionization rate

DTMROC-S: Deep submicron version of the readout chip for the TRT detector in ATLAS
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Abstract A new version of the circuit for the readout of the ATLAS straw tube detector, TRT [1], has been developed in a deepsubmicron process. The DTMROC-S is fabricated in a commercial 0.25 µm CMOS IBM technology, with a library hardened by layout techniques [

Batargeted for mobile multimedia
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Page 1. BASEBAND ANALOG CIRCUITS IN DEEP-SUBMICRON CMOS TECHNOLOGIES TARGETED FOR MOBILE MULTIMEDIA A Dissertation by VIJAYAKUMAR DHANASEKARAN challenges in deepsubmicron technology. The focus of this work is to develop low

Analysis of harmonic distortion in deep submicron CMOS.
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Abstract This paper presents a study of harmonic distortion measurement and modeling in an 0.14 um CMOS technology. Measurements and simulation of DC characteristics, as well

Decoupling Capacitance Estimation, Implementation, and Verification: A Practical Approach forDeep Submicron SoCs
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ABSTRACT The problem of dynamic variations in supply voltage and the related impact on chip performance is a major issue facing today's DSM SoC design teams. Through careful

Enhanced Velocity Overshoot and Transconductance in Si/Si0. 64Ge0. 36/Si pMOSFETs-Predictions for Deep Submicron Devices
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Abstract Electrical measurements have been carried out on Si/Si0. 64Ge0. 36/Si pMOS devices and it is demonstrated that enhanced low field carrier mobilities lead to concomitant and substantial enhancements in velocity overshoot and transconductance at deep

Shallow-trench-isolation bounded single-photon avalanche diodes in commercial deep submicron CMOS technologies
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Single-photon detection has gained increased relevance in recent years. It has found uses in diverse areas, including single-molecule dynamics [1], quantum communications [2, 3], military [4] and medical imaging [5], and biometrics [6]. Single photon detection is unique

Issues in high frequency noise simulation for deep submicron MOSFETs
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Abstract. This paper proposes issues in highly accurate high frequency noise simulation for deep submicron MOSFETs. Unlike classical RF design, in which a given device with fixed characteristics is used, CMOS RF design permits selection of user specified device ABSTRACT As circuit feature size continues to shrink, we will soon need a failure analysis technique that provides resolutions of 10 nanometers or less. This feasibility study concludes that AFM technology, with reasonable improvements, can take over where Abstract This article deals with the matching properties of MOS This article sets out to evaluate the MOS transistor mismatch transistors fabricated in a standard 0.18 gmmixed- signal in a standard 0.18, wn CMOS technology. It compares different CMOS process.

An energy-efficient high performance deep submicron instruction cache
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Abstract Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to

A Genetic Algorithm for Deep-Submicron MOSFET Parameters Extraction and Simulation
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Abstract Genetic algorithm is a stochastic-based optimization strategy with its randomly but systematically search strategy which is usually applied for solving complex problem, such as simulated model parameters extraction. To characterize the properties of MOSFET

Influence of Frequency-Dependent Characteristics on Deep Submicron Crosstalk Simulations
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Abstract The SIA Roadmap1shows a very aggressive drive to deep submicron designs. In this paper we discuss different approaches to the time domain simulation of crosstalk in deep submicron interconnects. We compare a technique based on frequency- Abstract In this work, a new IDDQ methodology, which is very suitable for testing deep submicron digital ULSI CMOS ICs, is proposed and demonstrated. It incorporates three new BICSs and has advantages of reduction in the circuit partitioning number, low input

Introduction to Deep Submicron CMOS Device Technology Its Impact on Circuit Design
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Loke et al. Avago Technologies Introduction to Deep Submicron CMOS Device Technology Its Impact on Circuit Design Alvin Loke, Tin Tin Wee, Mike Gilsdorf, Loke et al. Avago Technologies Deep Submicron FET Fabrication Sequence Well Implantation 2 n-well p-well

Investigation of Single-Cell Dynamic Faults in Deep-Submicron Memory Technologies
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Abstract: This paper presents single-cell dynamic fault models for deep-submicron semiconductor memories together with their associated tests (test primitives). The test primitives are evaluated industrially, together with the traditional tests, using 65nm

Deep submicron 65nm program Perspectives for the next generation satellites
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Abstract: This paper presents the recent advances in terms of European digital microelectronics technologies for space applications. This article exemplifies the case of the Deep Sub-Micron 65nm program led by ESA and CNES in partnership with

Noise diagnostics of advanced silicon substrates and deep submicron process modules
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Low-frequency (LF) noise consists of temporal fluctuations in the charge transport in semiconductor devices. As the transport is governed by carrier scattering and trapping events, it is evident that this parameter is potentially a very sensitive tool for studying

A novel approach to compact I–V modeling for deep-submicron MOSFET's technology development with process correlation
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The objective of this work is to develop a compact MOSFET model with minimum measurement data and model parameters as well as a one-iteration parameter extraction for deep-submicron MOS technology development. This has been achieved with our novel

Application of Hierarchical Transport Models for the Study of Deep Submicron Silicon MOSFETs
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Abstract In this paper, we present an integrated tool set with a hierarchy of transport models ranging from the driftdiffusion (DD), through various hydrodynamic (HD) to Monte Carlo (MC) models. Good agreement is achieved between experimental long-channel n-MOSEET

Relaxation of acceptance limits(RAL): a global approach for parametric yield control of 0. 1-µm deep submicron MOSFET devices
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Abstract-An alternative method to fixed quality acceptance limits for in-line yield control is proposed. Our study is based on a sensitivity analysis, which has revealed that conventional parametric yield-control techniques using fixed in-line acceptance (tolerance) limits, as

Comment on Nanometer resolution piezoresponse force microscopy to study deep submicron ferroelectric and ferroelastic domains† Appl. Phys. Lett. 94,
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In a recent article in this journal, Ivry et al. 1 report on the potential of piezoforce microscopy to investigate ferroelectric domain structures with very high spatial resolution. In the same paper, they describe the observation of nanometersized ferroelastic (a/c) domains in

Geometry-and Bias-Dependence of Normalized Transconductances in Deep SubmicronCMOS
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Geometry- and Bias-Dependence of Normalized Transconductances in Deep Submicron CMOS Matthias Bucher Technical University of Crete (TUC), Chania, Crete, GREECE level of inversion channel length. EKV 3.0 MOSFET model for deep submicron CMOS. Page 4.

deep submicron Vlsi



Effective power and ground distribution scheme for deep submicron high speed VLSIcircuits
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ABSTRACT This paper studies the power and ground distribution and its noise effect for deep submicron CMOS VLSI circuits. It is found that orders of magnitude reduction in switching noise can be achieved using an effective power and ground distribution scheme

Measurement and characterization of multi-layered interconnect capacitance for deep submicron VLSI technology
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V91 Proc. IEEE 1997 Int. Conference on Microelectronic Test Structures, Vol 10, March 1997. Measurement and Characterization of Multi-Layered Interconnect Capacitance for Deep Submicron VLSI Technology Dae-Hyung Cho, Man Ho Seung, Nam-Ho Kim, and

Design of Flip-Flops for High Performance VLSI Applications using Deep Submicron CMOS Technology
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Abstract This paper enumerates low power, high speed design of SET, DET, TSPC and C2CMOS Flip-Flop. As these flip flop topologies have small area and low power consumption, they can be used in various applications like digital VLSI clocking system,

Modeling of Inductive Interconnect Responses and Coupling Effects in Deep-Submicron VLSI
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Fig. 2.1 Various types of lumped RC interconnect models Fig. 2.2 Lumped and distributed R (L) C interconnect models Fig. 2.3 Cross-section of stacked interconnects Fig. 2.4 Single plate model Fig. 2.5 Optimally buffered interconnects (RC and RLC) Fig. 2.6 Gate driving

EE 382V–Computer-Aided Circuit Design for Deep Submicron VLSI Fall 2004
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This course reviews the major components of the modern computer-aided circuit design flow. An important motivation for the course is to explore the directions in which computer- aided circuit design evolves as it copes with the challenges brought about by the

Energy Efficient Advanced Low Power CMOS Design to reduce power consumption in Deep Submicron Technologies in CMOS Circuit for VLSI Design
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Abstract: Low power has emerged as a principal theme in today's electronic industry. Energy efficiency is one of the most critical features of modern electronic systems designed for high speed and portable applications. Reduction of power consumption makes a device more

VLSI Interconnect Characterization for Deep-Submicron Technology
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Abstract: Successful miniaturization of integrated circuit components has been the driving force behind the booming computer industry. When transistor structures are reduced in size, the switching time is also reduced, resulting in faster circuits. However, unfavorable results


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