dsp digital signal processing 2015







Efficient overlay architecture based on DSP blocks
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Abstract:Design productivity and long compilation times are major issues preventing the mainstream adoption of FPGAs in general purpose computing. Several overlay architectures have emerged to tackle these challenges, but at the cost of increased area and

Design of Fast Floating Point Multiply Accumulate Unit using Ancient Mathematics for DSPApplications
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ABSTRACT Digital Signal processing became an application to create high speed data processing systems like 3D rendering, 4G mobile internet, etc., we need best processors with high performance data path units and there is a growing need for research on

Design and Implementation of a FPGA and DSP Based MIMO Radar Imaging System
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Abstract. The work presented in this paper is aimed at the implementation of a real-time multiple-input multiple-output (MIMO) imaging radar used for area surveillance. In this radar, the equivalent virtual array method and time-division technique are applied to make 16

Speech Endpiont Detection Using DSP Builder
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Abstract: In this paper, we use DSP Builder to realize the speech signal endpoint detection based on short-time energy variation. In the design, we use the LUT (look-up table) window design and FSM (finite state machine) to simplify the hardware circuit and improve the

A hands-on DSP project mixing Entrepreneurial and technical concepts
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ABSTRACT Nowadays, industry is demanding engineers with entrepreneurial background. At Ohio Northern University, entrepreneurship mindset is becoming a crucial part of the curriculum. This paper suggests a hands-on DSP project that introduce students to

Research of 100Gbit/s DP-QPSK Based on DSP in WDM-PON System
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Abstract This paper introduces the DP-QPSK modulation coherent reception technology, the overall design and other key is sues for 100 Gbit/s DP-QPSK modulation. Using the technologies based on DSP, it realizes the long-range transmissions of 100 Gbit/s optical

Design Space Exploration of DSP Techniques for Hardware Software Co-Design: An OFDM Transmitter Case Study
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ABSTRACT This paper describes the exploration of design parameters for widely used Digital Signal Processing (DSP) algorithms and techniques. In this paper, some of the DSP algorithms and techniques are considered and executed them on soft core processors like

The Research of Lift Control System in Four-Point Platform Based on DSP
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Optimization of 64 bit Multiplier using Carry Save Adder and its DSP Application using Cadence
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Abstract: In this paper we have shown the design and implementation of multiplier in which carry save adder is used as an adder block for the addition of partial products of both multiplier and multiplicand as 64 bits and the product size is of 128 bit. Multiplication is the

Design of System for Electromechanical Equipment Condition Monitoring in Real-time Based onDSP and CPLD
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Abstract: A multi-parameters monitoring system is designed for mechanical and electric equipment which based on DSP and CPLD. Designing methods for hardware and software are introduced in this paper. In the system, powerful capability for numeric operation of

Filter Design Based on DSP Builder
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Abstract: Presents a method to realize FIR filter based on DSP Builder, FIR design using a relatively independent function of circuit module and subsystems in the design, it can easily realize the filtering function of FIR, simplified the design, modular design method greatly

MPPTSolar Photovoltaic (PV) Incremental Conductance Algorithm Maximum Power Point (MPP) Electrical Power Thermal Energy using DSP
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Abstract: A maximum power point tracking (MPPT) scheme is obligatory to ameliorate the efficiency of a solar photovoltaic (PV) panel. This paper proposes an ameliorated incremental conductance algorithm (InC) for tracking the maximum power point (MPP) of a

The real-time performance of a two-dimensional ANC barrier using a DSP and common audio equipment
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Summary The paper deals with a two-dimensional Active Noise Control (ANC) system in a linear setup to be used as an active sound barrier. Common audio equipment in combination with a Texas Instruments C6455 fixed point digital signal processor (DSP)

Resource Efficient Reconfigurable Processor for DSP Applications
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ABSTRACT--Reconfigurable processor will configure the architecture based on the application. In general processor consists of data path, control and memory unit. In proposed system CSLA (Carry Select Adder) with BEC (Binary to Excess Converter) and CSLA with

DSP Chip Architecture
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Page 1. DSP Chip Architecture Team Members: Steve McDermott Ken Whelan Kyle Welch Page 2. What Is Signal ProcessingengineeringHas many applications in other fields Page 3. What Is DSPDigital Signal ProcessingThis includes a wide variety of goals Page 4.

A Digital Thyristor Trigger Control System based on DSP
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Abstract. A digital trigger for three-phase fully-bridge thermistor, using a high performance DSP, is mainly introduced in this paper. This circuit can generate appropriate pulse triggering signals according to the control angle which is supplied by keyboard of DSP.

Review Paper on Implementation of DSP Unit in LEON3 Processor
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Abstract:LEON3 is a SPARC V8 processor developed by Gaisler Research. It is a synthesizable processor core for embedded applications. The LEON3 processor is part of the GRLIB package that is under continuous growth. To demonstrate the abilities of the

Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq
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ABSTRACT Coarse-grained overlay architectures have been shown to be effective when paired with general purpose processors, offering software-like programmability, fast compilation, and improved design productivity. These architectures enable general

IMPROVED MATRIX MULTIPLICATION USING MUX FOR HIGH SPEED DSP APPLICATIONS
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Abstract: Power consumption has become a critical concern in today's VLSI system design. The growing market for fast floating-point co-processors, graphics processors and digital signal processing chips has created a demand for high speed, area efficient multipliers.

A Discrete Scalar Projection method (DSP) for incompressible ows with variable density
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Abstract A new Scalar Projection method presented for simulating incompressible ows with variable density is proposed. It reverses conventional projection algorithm by computing first the irrotational component of the velocity and then the pressure. The first phase of the

TMS320C6713-DSP Based FSK Modem with Receiver Synchronisation
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TMS320C6713-DSP based communication testbed, designed for testing signal processing algorithms, channel measurements and performance analysis of digital receivers. As an example, the testbed is used to implement a frequency shift keying (FSK) modem with

High Speed Multiplication Using BCD Codes For DSP Applications
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Abstract:In digital systems, multiplier is the prominent deciding factor to the overall speed, area and power consumption. The intention of this project is to improve the parallel decimal multiplication. The proposed decimal multiplier uses internally a redundant BCD (Binary

Design of High Order Multi-precision for DSP Based Voltage Scaling Applications
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Abstract: In this paper, we present a multi-precision (MP) reconfigurable multiplier that constitutes variable precision, parallel processing (PP), to provide optimum performance for a variety of operating conditions. All of the building blocks of the proposed reconfigurable

Energy Efficient Approximate MAC Unit for High Speed DSP Application
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Abstract: In this paper a new energy efficient MAC unit will be introduced, which will reduce the hardware complexity and make justice with SPAA metrics. Another important issue in digital circuits besides speed, area, power consumption is accuracy. In this paper, our

A Pipelined Fused Processing Unit for DSP Applications
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Abstract This paper designs a processing element for FFT processor capable of operating on 32-bit double precision floating point numbers. Pipelining is performed on the computational elements of the DSP processor to enhance the throughput. The

Voice Based Database Management System Using DSP Processor
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Abstract:Security is provided to customers through PIN/ID protection, to secure their data and information using password. This method require user to authenticate them by entering password. There are cases of fraud and theft when people can easily know the password.

LOW POWER RADIX-10 MULTIPLICATION FOR DSP/MULTIMEDIA APPLICATIONS
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ABSTRACT: This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry save multioperand addition that uses a novel BCD 4221 recoding for decimal digits. It significantly improves the area

New VLSI Architecture for 64-bit MAC Unit for DSP Applications using SPST
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Abstract: In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic and low power. With the rapid advances in multimedia and communication system, high capacity signal processing are in demand, so High Speed

AREA EFFICIENT RADIX-10 MULTIPLICATION FOR DSP APPLICATIONS
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ABSTRACT: This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry save multioperand addition that uses a novel BCD 4221 recoding for decimal digits. It significantly improves the area

Design and Simulation of High Performance 32-Bit DSP Processor
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Abstract: With the advent of personal computer, smart phones, gaming and other multimedia devices, the demand for DSP processors in semiconductor industry and modern life is ever increasing. Traditional DSP processors which are special purpose (custom logic) logic,

DSP Algorithm based Enhanced Phase Locked Loop Scheme for DSTATCOM
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Abstract This paper deals with Enhanced Phase Locked Loop Control scheme for Distributed Static Compensator (DSTATCOM) in the distribution system. The proposed control scheme based DSTATCOM eliminates current harmonics, maintains unity power

DSP BASED SPEED SENSORLESS CONTROL USING INDUCTION MOTOR
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ABSTRACT Today, speed sensor less modes of operation are becoming standard solutions in the area of electric drives. The proposed algorithm has been implemented using a floating- point digital signal processor (DSP). Speed sensor-less control techniques can make the

Multi-stage Decimation and Multi-fold 50/60Hz Notch Filters for S Modulator Realized by 24-bit DSP
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Abstract: Magnetotelluric method is widely used in oil and gas exploration. The corresponding instrument system need to record low noise data at sample rate 2400Hz, 150Hz and 15Hz or other triple frequencies simultaneously. Notch filter is also need to

Search Performance In Peer To Peer Network-Survey Based On Dsp
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ABSTRACT Peer to peer networks form loosely tied application-level overlays on top of the Internet to help effective sharing of resources. Unstructured P2P networks can be constructed very proficiently without precise rules and so suitable to the Internet

Localization of an Ultrasonic Sound Source with DSP
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Abstract:Four receivers in an array where used to localise the direction of a source generating ultrasonic signals. The time delays of the incoming wave to the receivers were calculated, to determine the incoming angle. 181 discrete angles were analysed using a

Low Power Multiply Accumulate Unit (MAC) for DSP Applications
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Abstract: Wireless Sensor Network (WSN) presents significant challenges for the application of distributed signal processing and distributed control. These systems will challenge us to apply appropriate techniques to construct capable processing units with sensing nodes

Energy Efficient Multiplier for High Speed DSP Application
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Abstract: A multiplier is one of the important hardware blocks in most digital and high performance systems such as microprocessors. With improving in technology, many researchers have tried and are trying to design multipliers which offer high speed, low

A Novel DSP Controller Based PositionSpeed Control of BLDC Motor on MATLAB/SIMULINK
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Abstract: The project includes design and development of DSP Based Embedded digital controller for BLDC motor. The project involves literature survey of DSP processor applicable to motionspeed control. Also the project involves development of Brushless

Heterogeneous Work-stealing across CPU and DSP cores
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In this paper, we present HC-K2H, a programming model and runtime system for the Texas Instruments Keystone II Hawking platform, consisting of 4 ARM CPUs and 8 TI DSP processors. This System-on-a-Chip (SoC) offers high floating point performance with lower

DSP in image processing
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Abstract: Vision extracts useful information from images. Reconstructing the three- dimensional structure of our environment and recognizing the objects that populate it are among the most important functions of our visual system. Computer vision researchers

Faust audio DSP language in the Web
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Abstract With the advent of both HTML5 and the Web Audio API (a high-level JavaScript API for audio processing and synthesis) interesting audio applications can now be developed for the Web. The Web Audio API offers a set of fast predefined audio nodes as well as

DSP based high speed over current protection of power system with distributed generation
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Abstract In this paper, high speed over current protection is achieved by employing instantaneous over current digital relay using Variable Fractional Delay (VFD) filter. In this filter, real value of group delay and phase delay can be obtained. VFD filter is widely

Pursuance of 36-bit RISC processors in collaboration with application of DSP using FPGA
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Abstract:Abstract:RISC has become main stream in scientific and engineering applications. The demand for (DSP) has increased with advent of computer, smartphone, gaming and other multimedia devices. Today, FPGA s has become an important platform

AN OPTIMIZED IMPLEMENTATION OF 64-BIT MAC UNIT FOR DSP APPLICATIONS USING SPST
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Abstract: In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic and low power. With the rapid advances in multimedia and communication system, high capacity signal processing are in demand, so High Speed

RUNNING TITLE: EFFECT OF STEAMING ON DSP IN MUSSELS
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ABSTRACT The effect of industrial steaming on mussels that had been naturally exposed to DSP toxins for a long time, was studied using LC-MS/MS. The estimated toxicity increased with steaming in a percentage that cannot be explained by weight loss. The estimated

High Speed Reverse Converter Design Using Modified Hybrid Parallel Prefix Adders For DSPApplications
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Abstract-Residue number system is an unconventional number system that uses residues of a number in particular modulus for its representation. Major parts of RNS include forward converter, arithmetic unit and reverse converter. The reverse converter in the existing

BIT EFFICIENT RESIDUE NUMBER SYSTEM BASED LOW POWER RECONFIGURABLE DSPPROCESSOR
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Abstract In modern era of advanced computing and high end multimedia there is a need for low power reliable and portable electronic systems. Even though many techniques have been proposed to reduce power over the years, out of all, the best possible solution, so far

VLSI IMPLEMENTATION OF RADIX-10 MULTIPLICATION FOR DSP/MULTIMEDIA APPLICATIONS
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Abstract: This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry save multioperand addition that uses a novel BCD 4221 recoding for decimal digits. It significantly improves the area and

Design of 8-Bit RSFQ Based Multiplier for DSP Application
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Abstract: We have developed and experimentally evaluated at high-speed, a complete set of arithmetic circuits (multiply, add, and accumulate) for high performance digital signal processing (DSP). These circuits take advantage of the unique features of the Rapid

Design of High Order Multiprecision Multiplier for DSP Based Voltage Scaling Applications
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Abstract: In this paper, we present a multi-precision (MP) reconfigurable multiplier that constitutes variable precision, parallel processing (PP), to provide optimum performance for a variety of operating conditions. All of the building blocks of the proposed reconfigurable

Fast development of a DSP-based control of three-phase four-leg inverter for auxiliary power supply converters using hardware-in-the-loop
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Abstract-This paper presents an easy and relatively fast way to design and implement control system of three-phase four-leg inverter in DSP (digital signal processor). The inverter model is emulated using hardware-in-the-loop simulator and control system is coded in TI

Floating-Point Multiplier for DSP Using Vertically and Crosswise Algorithm
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Abstract:This paper presents a fast IEEE-754 single precision floating point multiplier. Multiplication of two floating point numbers which involves large dynamic range is critical requirement of various DSP applications. Vertically and crosswise algorithm is used for

Electric Vehicle Speed Control using Three Phase Inverter operated by DSP-based Space Vector Pulse Width Modulation Technique
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Abstract-Solar electric vehicles (SEV) are considered the future vehicles to solve the issues of air pollution, global warming, and the rapid decreases of the petroleum resources facing the current transportation technology. However, SEV are still facing important technical

A New Complex Floating-Point Representation Using Auto-Correlation Algorithm for DSPProcessors
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Abstract:Complex number computation is a big deal in mathematical calculations and it is well practiced in all modern processors, as we all familiar with real and imaginary parts in complex numbers, computation against the real and imaginary parts becomes a difficult

1V DSP IN WIRELESS COMMUNICATION SYSTEMS
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ABSTRACT: The requirements of the rapidly expanding second and third generation mobile communication systems place increasing demands on DSP algorithms and their implementations. This paper presents a survey of the implications of the new cellular

High Speed and Energy Efficient Approximate Adder for DSP Application
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Abstract: In this paper a new high speed Approximate Adder will be introduced, which will reduce the hardware complexity and make justice with SPAA metrics. Adders are one of the key components in arithmetic circuits. Approximation can increase performance or reduce

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