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low power VLSI research papers 2015



LOW POWER AND TEST DATA COMPRESSION IN VLSI TESTING USING NEW ENCODING SCHEME
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Abstract-Power dissipation during test is a significant problem as the size and complexity of systems-on-chip (SOCs) continue to grow. During scan shifting, more transitions occur in the flip-flops compared to what occurs during normal functional operation. This problem is

VLSI Implementation of 4X4 MIMO SC-FDMA Transceiver for Low Power Applications
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Abstract Single Carrier-Frequency Division Multiple Access (SC-FDMA) is an OFDMA alternative technology. SC-FDMA is the multiuser version of single carrier modulation with frequency domain equalization (SC/FDE). The main objective of SC-FDMA is to introduce

Single-ElectronTransistor Logic for High Reliability of Moore's Law and Low Power VLSI
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Abstract: The observation made in 1965 by Gordon Moore, co-founder of Intel, that the number of transistors that are embedded per square inch on integrated circuits had doubled every 18 months since the integrated circuit was invented. But as per latest trends in VLSI

Sub word Partitioning and Signal Value based Clock gating Scheme for Low Power VLSIApplications
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Abstract The low power optimization techniques are very crucial for next generation wireless communication and battery powered signal processing applications. Several low power optimization techniques at circuit level and device level were implemented in past two

AN ASYNCHRONOUS LOW POWER AND HIGH PERFORMANCE VLSI ARCHITECTURE FOR VITERBI DECODER IMPLEMENTED WITH QUASI DELAY
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Abstract: Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of

VLSI Designs for Low Power Applications
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Abstract:Low power has emerged as a principal theme in today's world of electronics industries. Power dissipation has become an important consideration as performance and area for VLSI Chip design. With shrinking technology reducing power consumption and

Circuit Optimization and Design Automation Techniques for Low Power CMOS VLSI Design: A Review
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Abstract Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under

To Develop and Implement Low Power, High Speed VLSI for Processing Signals using Multirate Techniques
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Abstract:-Multirate technique is necessary for systems with different input and output sampling rates. Recent advances in mobile computing and communication applications demand low power and high speed VLSI DSP systems [4]. This Paper presents Multirate

An Efficient Design of Optimized Low Power Dual Mode Logic Circuits Using VLSITechnology
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Abstract-This project represents a dual mode logic circuit for low power applications. Now a day's power consumption is the major role in chip design. If the area ofthe chip is reduced, the power consumption and the delays are increased due tosome effects like, cross talk,

Review on Low Power Design Using Comparator for VLSI Design Circuit
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ABSTRACT: The zone of low power and rapid planning of simple to-advanced converters (Adcs) has been a testing issue in the course of the most recent decade. The rate improvement of serial connections and the rising correspondence advances has slanted

VLSI IMPLEMENTATION OF LOW-POWER ADAPTIVE FIR FILTER USING DISTRIBUTED ARITHMETIC
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Abstract:The main objective is to design DA based adaptive filter in order to decreasing the logic complexity. Throughput is increasedby using parallel Look Up Table (LUT) update and concurrent implementation of filtering and weight-update operations. DA uses


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