RESEARCH PAPERS

serdes-serializer-deserializer research papers

A SerDes or serializer/deserializer is an integrated circuit (IC or chip) transceiver that converts parallel data to serial data and vice-versa. The transmitter section Wide range of SerDes drive long distances at multi-gigabit speeds with easy FPGA interface. A Serializer/Deserializer is a pair of functional blocks commonly used in high speed communications

SERDES Technology for Gigabit I/O Communications in Storage Area Networking.
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Abstract The paper reviews SERDES technology for storage area networking. A concept of a data switch is introduced to illustrate important role played by switching and backplane SERDES IC's. Selected stateof-the-art devices: 10 Gb/s line side SERDES and backplane The purpose of this paper is to address the manufacturing test of the digital part of an ASIC high speed Serializer Deserializer. This serdes contains both analog and digital cmos circuits which run with data rates up to 3.2 Gbps and clock frequencies up to 1.6 GHz. Combined with

Signals predict Serdes jitter behavior
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moves (closes), using both the frequency and amplitude of the jitter as factors. But the actual value for a specific Serdes must be measured experimentally. Intermediate-frequency behavior Interactions in the IF range tend to be complex. In this range, both clock and

25 Gbps SerDes
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Page 1. 25Gbps SerDes IEEE HSSG Meeting, Orlando FL March 13-15, 2007 Charlie Zhong, Cathy Liu and Freeman Zhong System Architecture, LSI Logic Page 2. 2 Outline Introduction 25G SerDes Design Considerations Different signaling schemes Equalization

Design of a Charge-Pump PLL for LVDS SerDes
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Abstract:A charge-pump PLL for low-voltage differential signaling (LVDS) serializer/deserializer (SerDes) is presented. A proposed charge pump can greatly reduced non-ideal effects, and a novel four-stage differential VCO using self-biasing improves

LVDS SERDES and DPA Block Diagram
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices 87 LVDS SERDES and DPA Block Diagram July 2012 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration LVDS SERDES and DPA Block Diagram The Arria II GX

Enhanced performance of SERDES current-mode output driver using 0.13 m PD SOI CMOS
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SERDES applications is implemented using 0.13 m Bulk and PD SOI CMOS technologies. Schematic simulation results confirm the enhanced performance of PD SOI for very high- speed interfaces. The PD SOI current-mode driver shows a 3 times lower data dependent

LVDS SERDES
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Figure 84 shows a transmitter and receiver block diagram for the LVDS SERDES circuitry in the left and right banks. This diagram shows the interface signals of the transmitter and receiver data path. For more information, refer to Differential Transmitter on page 811

Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement
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Abstract The IBIS Algorithmic Modeling Interface (IBIS-AMI) allows SerDes vendors to provide simulation models that run in multiple simulation environments. This has created the market for commercial SerDes channel simulators and raised the question of how well

Mini SerDes Based on Economic FPGA
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Abstract. SerDes has been widely used in high-speed serial interface in the past years, and it is often implemented as the form of ASIC and ASSP (application specific standard product, which is an integrated circuit that implements a specific function that appeals to a wide

A 10 Gb/s Equalizer in 0.18m CMOS Technology for High-speed SerDes
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Abstract. A 10 Gb/s equalizer consisting of analog equalizer and two-tap halfrate decision feedback equalizer (DFE) in a 0.18 m CMOS has been designer. By employing capacitive degeneration and inductive peaking techniques, the analog equalizer achieves large

Scalable Serdes Framer Interface (SFI-S) for 7 Series FPGAs
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Summary The Scalable Serdes Framer Interface (SFI-S) is an Optical Internetworking Forum (OIF) standard that defines the electrical connections between devices on a typical optical communications line card. An n-bit wide SFI-S configuration contains n data channels and

Reference System: PLB Gigabit Ethernet MAC with a SerDes Interface
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Summary This application note describes a reference system which illustrates how to build an embedded PowerPC system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core. This system has the PLB_Gemac configured to use Scatter/

SerDes Framer Interface Level 4 Phase 2
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Summary This application note describes the implementation of SerDes Framer Interface Level 4 Phase 2 (SFI4.2) in a Virtex-5 FPGA XC5VFX70T. The SFI4.2 standard is defined by the Optical Internetworking Forum (OIF) [Ref 1]. The OIF standard only specifies a 10 Gb/s interface.

SERDES Framer Interface Level 5 for Virtex-6 Devices
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SFI-5 is a fully synchronous system, meaning that there is only a single reference clock. For example, on the link from the FEC processor to the SERDES in Figure 1, the source reference clock is the same as the sink reference clock. This synchronization can be

An 8b/10b Encoding Serializer/Deserializer (SerDes) Circuit for High Speed Communication Applications Using a DC Balanced, Partitioned-Block, 8b/10b
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Abstract:In this paper, an 8b/10b encoding serializer/deserializer (SerDes) circuit using a DC-balanced, partitioned block, 8b/10b transmission code was presented. The information format of this transmission code consists of packets which are variable in length and can

A High-Speed 64b/66b Decoder Used in SerDes
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A high-speed 64b/66b decoder for SerDes system was designed in TSMC 0.18-m CMOS Technology. The chip is composed of Block Sync, Descrambler, Decode Process and Receive Control. To make the system can be work in high speed, we use a lot of

SerDes Channel Simulation in FPGAs Using IBIS-AMI
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Over the past several years, high-speed FPGA interfaces have moved from fast LVDS at frequencies of up to 1.6 Gb/s, to very-high-speed serial interfaces of up to 3.125 Gb/s (PCIe

Design of 10 Gb/s Bidirectional SerDes Integrated with TRx for Chip-to-chip Optical Link
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Abstract In the context of technology scales down and processing speed increases, the electrical interconnections are considered as the bottle-neck of the high-speed signal transmission between chips, especially the large data width transmission between CPU (

Multi-Rate SerDes Transceiver for IEEE 1394b Applications
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Abstract? This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A phase interpolator based clock and data

A Regulator Design for a SerDes PHY of a High Speed Serial Data Interface
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Abstract:A fully integrated 3.3 V-to-1.2 V supply voltage regulator for application in IEEE 1394B PHY has been designed in 0.13 m SMIC Mixed Signal process technology. The regulator is able to deliver peak current transient of 300 mA, while the output voltage

SERDES Framer Interface Level 5
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SFI-5 is a fully synchronous system, meaning that there is only a single reference clock. For example, on the link from the FEC processor to the SERDES in Figure 1, the source reference clock is the same as the sink reference clock. This synchronization can be

EXTERNAL: 42 LINK: EXTERNAL SERDES: ASIC: SERDES
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1. Field of the Invention The present invention relates to data processing systems, and more particularly, to bridge systems including mecha nisms for transferring information betWeen buses. 2. Description of Related Art Computers can use buses to transfer data betWeen a


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