RESEARCH PAPERS

verilog research papers recent 2014




Verilog-A Compact Model for Oxide-based Resistive Random Access Memory (RRAM)
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RRAM compact model capable of simulating real-time DC cycling and pulsed operation device behavior, including random variability that is inherent to RRAM. This paper illustrates the physics and capabilities of the model. The model is verified using different sets of

DESIGN AND IMPLEMENTATION OF I2C SINGLE MASTER ON FPGA USING VERILOG
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Abstract: This paper focuses on the design of I2C single master which consists of a bidirectional data line ie serial data line (sda) and serial clock line (scl). This protocol has the ability to support multiple masters. I2C is a two-wire, bidirectional serial bus that provides

Design and Implementation of a Fast Unsigned 32-bit Multiplier Using Verilog HDL
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Revised: 22/04/2014 Accepted: 16/05/May 2014 Published: 31/05/2014 Abstract: This project deals with the comparison of the VLSI design of the carry look-ahead adder (CLAA) based 32-bit unsigned integer multiplier and the VLSI design of the carry select adder (

SPEED AND AREA OPTIMIZED REALIZATION OF 5 PORT ROUTER USING VERILOG HDL
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The router is a" Network Router" has a one input port from which the packet enters. It has five output ports where the packet is driven out. Packet contains 2 parts. They are Header, and data. Packet width is 8 bits and the length of the packet transferring can be between 1

Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface
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Abstract:A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of
A widely used advanced microprocessor bus architecture (AMBA) aims at easing the component design by using the combination of interchangeable components in the system- on-chip (SoC) designs (ARM Ltd., 1999). This paper presents the implementation and

A Verilog Compiler Proposal for VerCPU Simulator
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Abstract:Verilog is a widely used Hardware Description Language (HDL) for VLSI design and modeling. As a language developed with hardware execution concurrency in mind, Verilog can be mapped onto a dedicated processor for higher simulation throughput. The

Proficient FPGA Execution of Secured and Apparent Electronic Voting Machine Using VerilogHDL
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Abstract Electronic Voting Machine is an electronic voting device used for conducting the parliamentary elections electronically. It consists of two units that can be inter-linked; a ballot unit which a voter uses to exercise his vote and a control unit which used by the polling

Verilog HDL Implementation of a Universal Synchronous Asynchronous Receiver Transmitter
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Abstract:This paper presents the Verilog HDL implementation of a Universal Synchronous/ Asynchronous Receiver/Transmitter (USART). The proposed design exhibits enhance power efficiency compared to the standard USART 8251a, which dissipates 48.2462 µW. 308 18 System Verilog Assertionsz LAB Answers 18.5 LAB5: Answers : Data Transfer Protocol (Fig. 18.8) LAB Overview I Specification for a simple data transfer protocol. dvalid must remain asserted for minimum of 2 clocks but no more than 4 clocks. 'data' must be known when '

Analysis of Different Bit Carry Lookahead Adder with Reconfigurability in Low Power VLSI Using Verilog Code
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ABSTRACT: Fast addition plays an important role in advanced digital system. Recently, reconfigurable adders have been widely employed to achieve real time processing of media signals. This paper presents a design-forreconfigurability (DFR) technique for carry look

IMPLEMENTATION OF A VERILOG-BASED DIGITAL RECEIVER FOR 2.4 GHZ ZIGBEE APPLICATIONS ON FPGA
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Abstract This paper presents the implementation of a digital receiver for 2.4 GHz Zigbee IEEE 802.15. 4 applications on a Spartan3E XC3S500E field programmable gate array (FPGA). The proposed digital receiver comprises an offset quadrature phase shift keying (

Verilog Implementation of Parallel AES Encryption Engines for Multi-Core Processor Arrays
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Abstract: Advanced Encryption Standard (AES) has been lately accepted by NIST as the symmetric key standard for encryption and decryption of blocks of data. In encryption, the AES accepts a plaintext input, which is limited to 128 bits, and a key that can be specified

Design and Implementation of USB Transceiver with Verilog
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Design of Multisized Output Cache Controller using Verilog
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Abstract: This paper describes the design of a Multi-sized Output Cache Controller that will handle 2Kbyte 16 ways with 4 word block size cache. A cache controller is a device that used to sequence the read and write of the cache storage array. Most of modern

ETHERNET IP CORE VERIFICATION USING SYSTEM VERILOG HDL
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Abstract:Functional verification of IP is an essential process in the chip/System on Chip (SoC) design process, since this would ensure correct functionality of the IP with the SoC. This paper intends to highlight the functional verification process of an Ethernet IP core,

High Speed and Power Optimized Parallel Prefix Modulo Adders using Verilog
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Abstract: The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and microprocessor data path units. As such, extensive research continues to be focused on improving the power delay performance of the adder.

AN EFFICIENT IMPLEMENTATION OF AUTOMATIC WASHING MACHINE CONTROL SYSTEM USING VERILOG
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ABSTRACT As described by digital system the language Verilog HDL is widely used in the circuit design, has its own advantages to be able to used as software language which describes hardware features that makes it efficient and has good readability, portability,

Implementation of MAC Unit with Reduced Delay and Power using Verilog-HDL
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Abstract: A design of high performance 64 bit Multiplier-and-Accumulator (MAC) is implemented in this paper. MAC unit performs important operation in many of the digital signal processing (DSP) applications. The main objective of this project is to design and

DESIGNING OF INTER INTEGRATED CIRCUIT USING VERILOG
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ABSTRACT This paper primarily deals with the designing of inter integrated circuit (I2C) using verilog in Modelsim-Altera 6.4 a (Quartus 2nd edition 9.0). The I2C Bus is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission

Realization of 32-Bits Carries Select Adder using Verilog
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Abstract: Design of power-efficient and high-speed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for

Including the Promiscuous mode in the design of MAC controller based on AXI bus and Verification with System Verilog
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Abstract: Integrated circuits have entered the era of System-on-a-Chip (SoC), which refers to integrating all components of a computer or other electronic system into a single chip. With the increasing design size, IP is an inevitable choice for SoC design. And the widespread

verilog research papers 2012



The VTR project: architecture and CAD for FPGAs from verilog to routing
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ABSTRACT To facilitate the development of future FPGA architectures and CAD tools--both embedded programmable fabrics and pure-play FPGAs--there is a need for a large scale, publicly available software suite that can synthesize circuits into easily-described 

An efficient IEEE754 compliant floating point unit using verilog
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A floating-point unit (FPU) colloquially is a math coprocessor, which is a part of a computer system specially designed to carry out operations on floating point numbers . Typical operations that are handled by FPU are addition, subtraction, multiplication and division. 

Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs
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ABSTRACT In this paper, we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient verification of Image Signal Processing IP's/SoC's. With the tight schedules on all projects it is important to have 

Optimization of multi-channel HDLC protocol transceiver using Verilog
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ABSTRACT To transmit and receive data at high speed in any network without any error a protocol is required. HDLC protocol of layer-2 of OSI model which is most suitable for bit oriented packet transmission mode is discussed in this article. HDLC protocol was 

Mean-Shift Algorithm: Verilog HDL Approach
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ABSTRACT TheABSTRACT should summarize the contents of the paper and should Object tracking algorithms, when it comes to implementing it on hardware ASIC, it becomes difficult task, due to certain limitations in hardware. This paper shows how mean-shift algorithm is 

A Verilog-A model for silicon nanowire biosensors: From theory to verification
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ABSTRACT Silicon nanowires offer great potential as highly sensitive biosensors. Since the signals they produce are quite weak and noisy, the use of integrated circuits is preferable to read out and digitize these signals as quickly as possible following the sensing event to 

FPGA Implementation of an Advanced Traffic Light Controller using Verilog HDL
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ABSTRACT Traffic lights are the signaling devices used to manage traffic on multi-way road. These are positioned to control the competing flow of the traffic at the road intersections to avoid collisions. By displaying lights (red, yellow and green), they alternate the way of 

Efficient Implementation of 16-Bit Multiplier-Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog
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ABSTRACT In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse 

A Hybrid Verilog-A and Equation-defined Subcircuit Approach to MOS Switched Current Analog Cell Simulation
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ABSTRACT Conventional modeling and simulation of two-phase switched current MOS- integrated circuits is normally undertaken at semiconductor device level. This allows primary and secondary circuit effects to be studied and characterized. However, with the growing 

Behavioural model of Spin Torque Transfer Magnetic Tunnel Junction, Using Verilog-A
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ABSTRACT A novel simple and efficient model of Spin Torque Transfer Magnetic Tunnel Junction (STT-MTJ) is presented. The model is implemented using Verilog-A. The model accurately emulates the main properties of an STT-MTJ which includes Tunnel Magneto 

Design of A Keyless Coded Home Lock System Using Verilog Hardware Description Language
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ABSTRACT This paper presents the design of a keyless coded home loack system using Verilog HDL. The system allows a house owner to enter a numeric combination code on a push button keypad. The door of the house will only unlock if the code entered matches 

Embedded SoPC Design with NIOS II Processor and Verilog Examples
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Explores the unique hardware programmability of FPGA-based embedded systems, using a learn-by-doing approach to introduce the concepts and techniques for embedded SoPC design with Verilog An SoPC (system on a programmable chip) integrates a processor, 

Vdiff: a program differencing algorithm for Verilog hardware description language
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ABSTRACT During code review tasks, comparing two versions of a hardware design description using existing program differencing tools such as diff is inherently limited because these tools implicitly assume sequential execution semantics, while hardware description 

Design and Functional Verification of A SPI Master Slave Core Using System Verilog
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ABSTRACT Synchronous serial interfaces are widely used to provide economical board level interfaces between different devices such as microcontrollers, DACs ADCs and other. Many IC manufacturers produce components that are compatible with SPI and Microwire/plus. 

Verilog Implementation of FPGA Based DSP Design like FFT Processors
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ABSTRACT Implementing hardware design in Field Programmable Gate Arrays (FPGAs) is a formidable task. There is more than one way to implement the DSP design for FFT processor and digital FIR filter. Based on the design specification, careful choice of implementation 

Design and modeling of a continuous-time delta-sigma modulator for biopotential signal acquisition: Simulink vs. Verilog-AMS perspective
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ABSTRACT In the current trend of short time-to-market and complex circuits and systems containing billions of nanoscale transistor, fast and accurate time-domain simulations are crucial for analog and mixed-signal (AMS) design and verification. This will ensure 

System-on-chips Design Using ISCAS Benchmark Circuits-An Approach to Fault Injection and Simulation Based on Verilog HDL
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ABSTRACT The evolution of the embedded cores-based design paradigm in recent times has created numerous challenging problems for the test design community. To develop suitable test environment and appropriate test methodologies for digital cores-based system-on- 

Design and Implementation of Automatic Train Ticketing System Using Verilog HDL
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ABSTRACT Automatic Train Ticketing System (ATTS) dispense train tickets at railway stations in the absence of salespersons. ATTS has been implemented in many countries as the number of passengers increases day by day, but not yet in Pakistan. In Pakistan 

Digitally Assisted Backend Correction Pipeline ADC Verilog-A Modeling
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ABSTRACT In this paper, a 12 bits pipeline ADC (analog to digital converter) based on digitally assisted backend correction is described and behaviorally modeled in Verilog-A language. The Verilog-A model is simulated with Cadence Spectre simulator. In the traditional use of 

Mechanical Approach to Linking Operational Semantics and Algebraic Semantics for VerilogUsing Maude
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ABSTRACT Verilog is a hardware description language (HDL) that has been standardized and widely used in industry. It contains interesting features such as event-driven computation and shared-variable concurrency. This paper considers how the algebraic semantics links 

Verilog-a compact semiconductor device modelling and circuit macromodelling with the QucsStudio-ADMS turn-key modelling system
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ABSTRACT The Verilog-A Analogue Device Model Synthesizer(ADMS) has in recent years become an established modelling tool for GNU General Public License circuit simulator development. Qucs and ngspice being two examples of open source circuit simulators that 

IP CORE DESIGN OF MICROCONTROLLER SYSTEM USING VERILOG FOR ROBOT BASED AGRICULTURAL IMPLEMENTS
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ABSTRACT This paper presents an RTL compliant Verilog IP Core design of a Microcontroller System modeled on the popular 8051 of Intel. This requirement primarily stems from the on-going project to design a Robot based Agricultural Implement. The 

Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration
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ABSTRACT Current Verilog-AMS system level modeling does not capture the physical design (layout) information of the target design as it is meant to be fast behavioral simulation only. Thus, the results of behavioral simulation can be very inaccurate. In this paper a paradigm 

Comparison of ABM SPICE Library with Verilog-A for Compact CNTFET Model Implementation
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ABSTRACT In this paper we have implemented the semi-empirical compact model for CNTFETs already proposed by us both in SPICE, using ABM library, and in Verilog-A in order to compare them. Typical analogue circuits and logic blocks have been simulated and results have 

Design synthesizable USB 3.0 using Verilog HDL and simulate design using Cadence
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ABSTRACT In this project I design USB 3.0 using Verilog HDL and simulate the design in Cadence. My design mainly includes two layers of USB 3.0, Physical Layer and Link Layer. Along with USB 2.0 functionality it includes Superspeed functionality. Physical Layer 

AUTOMATED DEBUGGING OF VERILOG DESIGNS
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In this article we report on novel insights in model-based software debugging of hardware description languages (HDLs). Today's simulation driven working process emphasizes the need for exploiting test suites not only for detecting but also for localizing the root cause of 

Visualization of verilog digital systems models
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ABSTRACT Nowadays the digital systems design is almost exclusively realized using hardware description languages (HDL). Verilog belongs to the HDLs that are the most widespread especially in the United States. However, the textual HDL representation of structural 

Realization Of An 8-bit Pipelined Microprocessor in Verilog HDL
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ABSTRACT Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub process being divided segment that operates concurrently with all other segments. A pipeline may be visualized as a collection of processing segments through 

Verilog Tutorial
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Comments–Verilog comments are the same as in C++. Use//for a single line comment or for a multiline comment.• Punctuation–white spaces are ignored in Verilog. A semicolon is used to indicate the end of a command line and commas are typically used to 

A hardware implementation of VHASH, a universal hashing algorithm using System Verilog
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ABSTRACT Hacking and Phishing are major threats in today's informational world. Information security is a major concern for Information Technology (IT) specialists. Hackers and other untrusted parties try to access the confidential information using different hacking 

The ASIC Design and Verification Based on Verilog HDL
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ABSTRACT Logic design and verification is the frontend of ASIC (Application Specific Integrated Circuit), and is a very important design part during the design process of ASIC. A Verilog HDL design case-2× 2 SDH digital cross-connect matrix is provided to illustrate the entire 

Implementation of Pipelined Data Encryption Standard for Security Enhancement through Verilog
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ABSTRACT This paper specifies a cryptographic algorithm in order to protect sensitive data. To maintain the data confidentially and to protect it, we need to convert the data into different form that differs completely from input and then transmit it. That data has to be again 

Compact modeling of circuits and devices in Verilog-A
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The compact model of a circuit or device is a system of linear and/or nonlinear differential equations that effectively models the behavior of the circuit or device. Compact modeling plays a critical role in circuit simulation, because in order to simulate a circuit with a 


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