RESEARCH PAPERS

vlsi identification research papers



Identification of optimal link redundancy for which a given fault pattern is catastrophic in VLSIlinear arrays
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In a linear array of N processing elements, one faulty element is sufficient to stop the flow of information from one side to the other. Without the provision of fault-tolerance capabilities, the yield of VLSI chips for such an architecture would be so poor that its production would 

Design and Implementation of VLSI Architecture for Characteristic Identification of Binary Pulse Compression Sequence
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ABSTRACT This paper describes the VLSI implementation for identification for of characteristic parameter of the given binary pulse compression sequence. In this paper an efficient VLSI architecture is proposed to calculate the characteristic parameter of the binary pulse 

A VLSI based Virtual Instrumentation for Low Cost Induction Motor Parameter Identification
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ABSTRACT The steady state equivalent circuit parameters are essential for diagnosing the condition of an induction motor . These parameters could be determined, with a good accuracy, through specific tests, but the procedure is time consuming and off line 

VLSI Implementation of DIP Based Edible Oil Adulteration Identification
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ABSTRACT Authentication is of paramount importance in the food industry where incoming batches of raw materials and finished products must be tested for compliance with regulatory and health specifications. The recent dioxin crisis highlighted the importance of checking 

fpga identification



FPGA Implementation of a recurrent neural fuzzy network with on-chip learning for prediction and identification applications
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In this paper, a hardware implementation of a recurrent neural fuzzy network (RNFN) used for identification and prediction is proposed. A recurrent network is embedded in the RNFN by adding feedback connections in the second layer, where the feedback units act as 

FPGA Implementation of NLMS Algorithm for Identification of unknown system
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ABSTRACT This paper proposes a VHDL implementation of a variable step size Least Mean Square (NLMS) adaptive algorithm. The envisaged application is the identification of an unknown system. The good convergence of NLMS algorithm has made us to choose it. It 

New Directions for FPGA IP Core Watermarking and Identification
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ABSTRACT In this paper, we present an overview of new watermarking and identification techniques for FPGA IP cores. Unlike most existing watermarking techniques, the focus of our techniques lies on ease of verification, even if the protected cores are embedded into 

Identification of Critical Variables using an FPGA-based Fault Injection Framework
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ABSTRACT The shrinking nanometer technologies of modern microprocessors and the aggressive supply voltage down-scaling drastically increase the risk of soft errors. In order to cope with this risk efficiently, selective hardware and software protection schemes are 

Real Time Noise Source Identification System using Field Programmable Gate Array (FPGA) Technology
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K Veggeberg, A Zheng ,scitation.aip.org ABSTRACT Acoustic beamforming is usually used as an off-line analysis tool for noise source identification (NSI). The computational requirements of beamforming make real-time processing difficult to achieve in conventional NSI measurement systems. This limitation 

Identification of Trojans in an FPGA using Low-Precision Equipment
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Thanks to recent research in the field, the awareness of the threat known as' Hardware Trojans' has grown. This is a key issue, as there is a standing assumption in circuits that'the hardware is safe'. Unfortunately, this is not always the case, as there are many 

Intelligent License Plate Positioning Identification System Based on FPGA
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HC Xie, M Zhou, P Zhang ,innovateasia.com ABSTRACT With the rapid development of China's national economy, intelligent transportation systems has become the main direction of the development of traffic management, and license plate recognition system technology as the core of intelligent transportation system 

FPGA based Optimisation and Implementation of Nondestructive Identification Procedures
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S Uting, M Brutscheck, S Becker, AT Schwarzbacher ,usb.issc.ie ABSTRACT The correct and fast identification of unknown ICs is an important issue for current as well as future IC technology. The authors have previously presented an algorithm which has demonstrated for the first time the correct non-invasive identification of unknown ICs [1 

Methods for Dynamic Identification of Program Control-Flow Structures for FPGA-based Systems
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ABSTRACT Continuous advances made in the field of embedded systems have lead to a time where a small chip has to be capable of high-speed processing and saving as much energy as possible. A way of achieving these objectives is by extending microprocessors with 

vhdl research papers 2012




VHDL Design for Image Segmentation using Gabor filter for Disease Detection
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ABSTRACT Tonsillitis, Tumor and many more skin diseases can be detected in its early-state and can be cured. For this a new idea for efficient Gabor filter design with improved data transfer rate, efficient noise reduction, less power consumption and reduced memory 

Design of fixed-point rounding operators for VHDL-2008
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Besides floor (round towards-8) and ceil (+8), it also defines fix (zero), round (nearest; ties to+8), nearest (nearest; ties to greatest absolute value) convergent (nearest; ties to closest even) Supported by the MATLAB HDL Coder GraphLab, AccelDSP (discontinued) and 

FPGA-Based BASK and BPSK Modulators Using VHDL: Design, Applications and Performance Comparison for Different Modulator Algorithms
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ABSTRACT This paper presents the simulation results of binary digital modulation schemes. In this paper, for BASK and BPSK modulation techniques used FPGA algorithm, multiplier don't using. If multiplier block is used for multiplication bit stream with carrier signal, used 

Implementation of a temperature dependent magnetic model in Simplorer using VHDL-AMS language
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ABSTRACT This paper presents a study based on the work done to create a temperature dependent magnetic model able to represent the dynamic behavior of magnetic materials. This model is developed using system simulation software (Simplorer) and hardware 

Development of a Parallel Image Processing Architecture in VHDL
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ABSTRACT Image processing tasks such as filtering, stereo correspondence and feature detection are inherently highly parallelisable. The use of FPGAs (Field Programmable Gate Arrays), which can be operated in highly parallel configurations, can thus be a useful 

VHDL Environment for Pipeline Floating Point Arithmetic Logic Unit Design and Simulation
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A pipeline floating point arithmetic logic unit (ALU) design using very high speed hardware description language (VHDL) is introduced. The novelty of the ALU is it gives high performance through the pipelining concept. Pipelining is a technique where multiple 

Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code
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ABSTRACT A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design 

VHDL Implementation of Efficient Multimode Block Interleaver for WiMAX
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ABSTRACT Wireless communication is one of the most vibrant research areas in the communication field today. WLAN and WiMAX are emerging standards for wireless broadband communication system. OFDM is multiplexing technique used in above 

Design and Implementation of I2c master controller on FPGA using VHDL
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ABSTRACT The focus of this paper is on I2C protocol following master controller. This controller is connected to a microprocessor or computer and reads 8 bit instructions following I2C protocol. The instructions are then processed and converted to instructions which follow 

VHDL IMPLEMENTATION OF TEST ACCESS PORT CONTROLLER
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ABSTRACT In this paper, an implementation of IEEE 1149.7 standard is used for designing Test Access Port (TAP) Controller and testing of interconnects is done using boundary scan. By c-JTAG the pin count gets reduced which increases the performance and simplifies the 

A NEW VLSI ARCHITECTURE OF PARALLEL MULTIPLIER BASED ON RADIX-4 MODIFIED BOOTH ALGORITHM USING VHDL
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ABSTRACT Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually 

THE DESIGN OF DIGITAL FREQUENCY SYNTHESIZER BASED ON VHDL
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ABSTRACT Direct digital frequency synthesizer (DSS) was proposed by Tiemey at 1971 and this frequency synthesis technique soon came to the attention of people because of its good frequency resolution and fast frequency performance. Now, it is extensively used in 

Encryption Design Based on FPGA using VHDL
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ABSTRACT There is a quiet, international battle underway, a battle that impacts every data consumer and producer. The important part of this battle are the cryptographers who work to protect our national security and the privacy of our personal information through 

VHDL Implementation of 8-Bit ALU
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ABSTRACT In this paper VHDL implementation of 8-bit arithmetic logic unit (ALU) is presented. The design was implemented using VHDL Xilinx Synthesis tool ISE 13.1 and targeted for Spartan device. ALU was designed to perform arithmetic operations such as addition and 

VHDL Design and FPGA Implementation of a Parallel Reed-Solomon (15, K, D) Encoder/Decoder
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ABSTRACT In this article, we propose a Reed Solomon error correcting encoder/decoder with the complete description of a concrete implementation starting from a VHDL description of this decoder. The design on FPGA of the (15, k, d) Reed Solomon decoder is studied and 

Class 15 VHDL Introduction
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-- majority vote ENTITY majority_vote IS PORT( a, b, c: IN BIT; y : OUT BIT); END majority_vote; ARCHITECTURE maj_vote OF majority_vote IS BEGIN y = (a and b) or (b and c) or (a and c); END maj_vote;  -- This is comment ENTITY logic_circuit IS PORT( a, b, 

VHDL Capture Guidelines
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ABSTRACT This document sets guidelines for the development of digital designs (circuits) and their subsequent capture with a Hardware Description Language (HDL); specifically, VHDL. This document is a guideline intended to be enforced by the design team with appropriate 

Integration of existing optimisation techniques with the DWARV C-to-VHDL compiler
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ABSTRACT Hardware acceleration using reconfigurable devices is a hot research item. To facilitate this acceleration technique, also called reconfigurable computing, tools are being developed that translate High-Level Languages into Hardware Description Languages. 


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