RESEARCH PAPERS

vlsi research papers 2013




Application of Galois Field in VLSI Using Multi-Valued Logic
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ABSTRACT Multi-valued logic is an apparent extension of binary logic where any proposition can have more than 2 values. Interconnections play a crucial role in deep sub-micron designs because they dominate the power and area. Design of the binary logic circuits is 

ECE 538: VLSI System Testing
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Select a project from the list below, or propose a new project. You must complete a project in order to receive a grade in this course. Projects may be proposed by individual students or by a team of two students. (The latter is recommended only for large programming or design 

Conference 8764: VLSI Circuits and Systems VI
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Plastic optical fiber has become one of the most preferred choices, more than copper cables, for low-cost high-speed communications because it is lighter, reliable and cheaper. However, it has the same limitation in bandwidth which can cause, along with other factors 

VLSI Design Of Secure Cryptographic Algorithm
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ABSTRACT Lightweight cryptography (LWC) is an emerging research area which has to deal with the trade-off among security, cost, and performance. In this paper we present the idea and list some types of LWC algorithms. Hummingbird is a novel ultra lightweight 

VLSI Design of Configurable Integer Pixel Motion Estimation with a Reservoir Architecture
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ABSTRACT A scalable VLSI architecture for Variable Block Size Motion Estimation (VBSME) in H. 264/AVC based on a full-search motion estimation algorithm is proposed in this paper. Through rational design for the data flow and processing module array, the memory traffic 

VLSI Design of Pipelined R2MDC FFT for MIMO OFDM Transceivers
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ABSTRACT In this study, an area-efficient low power FFT (Fast Fourier Transform) processor is proposed for MIMO-OFDM (Multi Input Multi Output-Orthogonal Frequency Division Multiplexing) that consists of a modified architecture of radix-2 algorithm which is 

Application of Sparse Tensors for Optimizing Multi-Dimensional VLSI Electromagnetic Analysis
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ABSTRACT Electromagnetic analysis of VLSI layout results in sparse matrices which have to be solved to calculate the capacitance of nodes. Modern semiconductor manufacturing involves many photo-lithography and chemical processes which induce in-die process variation [1, 

VLSI Implementation of DIP Based Edible Oil Adulteration Identification
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ABSTRACT Authentication is of paramount importance in the food industry where incoming batches of raw materials and finished products must be tested for compliance with regulatory and health specifications. The recent dioxin crisis highlighted the importance of checking 

VLSI Design of Configured Fractional Pixel Motion Estimation with a Small Cache
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ABSTRACT This paper proposes a circuit structure suitable for H. 264 full search variable block fractional pixel motion estimation. Analyze the principle of fractional pixel motion estimation and complete the VLSI design. This architecture designs 32× 32 size of the searching 

High-Performance VLSI Architecture of H. 264/AVC CAVLD by Parallel Run_before Estimation Algorithm
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A high-performance VLSI architecture for the H. 264/AVC context-adaptive variable-length decoder (CAVLD) is proposed in order to reduce the computation time. The overall computation is pipelined, and a parallel processing is employed for high performance. For 

VLSI Implementation of H. 264 Transform and Quantization Algorithms
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ABSTRACT In this paper, we present a high performance and low cost hardware architecture for real-time implementation of forward transform and quantization and inverse transform and inverse quantization used in H. 264/MPEG4 Part 10 video coding standard. The 

MULTI-AGENT PARALLEL IMPLEMENTATION OF VLSI CAD PROCEDURES
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Summary The integrated framework for parallel processing of data describing integrated circuits layouts that based on a graphoriented parallel algorithm representation is represented. A parallel program is developed from single computational units (grains) in 

Efficient FM Algorithm for VLSI Circuit Partitioning
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ABSTRACT In FM algorithm initial partitioning matrix of the given circuit is assigned randomly, as a result for larger circuit having hundred or more nodes will take long time to arrive at the final partition if the initial partitioning matrix is close to the final partitioning then the 

Comparison of 90nm and 65nm Logic Synthesis of a SAD Configurable VLSI Architecture
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ABSTRACT This paper evaluates the impact of the technology node on the area, performance and power consumption of a configurable VLSI architecture for Sum of Absolutes Differences (SAD). Such architecture may be configured to take benefit from pel 

A Survey on Brain–Machine Interface used in VLSI Field-Programmable Mixed-Signal Array
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ABSTRACT A very large scale integration field-programmable mixed-signal array specialized for neural signal processing and neural modeling has been designed. This has been fabricated as a core on a chip prototype intended for use in an implantable closed-loop 

Hardware-Optimized Lattice Reduction Algorithm for WiMax/LTE MIMO Detection using VLSI
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ABSTRACT This paper presents the first ASIC implementation of an LR algorithm which achieves ML diversity. The VLSI implementation is based on a novel hardware-optimized LLL algorithm that has 70% lower complexity than the traditional complex LLL algorithm. 

IMPLEMENTATION OF VLSI BASED IMAGE COMPRESSION APPROACH ON RECONFIGURABLE COMPUTING SYSTEM-A SURVEY
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ABSTRACT Image data require huge amounts of disk space and large bandwidths for transmission. Hence, image compression is necessary to reduce the amount of data required to represent a digital image. Therefore efficient technique for image compression 

Partitioning in 3D VLSI Physical Design–A Brief Survey
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ABSTRACT Partitioning plays an increasingly very important role in the physical design process of VLSI circuits and systems. There are partitioning problems to be solved on all levels ofAbstraction. The available algorithm technology determines how effectively we 

Vlsi Implementation of Low Power Convolutional Coding With Viterbi Decoding Using Fsm
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ABSTRACT Convolution Encoding with Viterbi Decoding is a powerful method for Forward Error correction and Detection. It has been deployed in many Wireless Communication Systems to improve the limited capacity of the Communication channels. Forward Error 

ELE-863 VLSI Circuits and Systems for Data Communications
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F Yuan, P Eng ,ee.ryerson.ca Page 1. ELE-863 VLSI Circuits and Systems for Data Communications Interconnects Fei Yuan, Ph.D, P.Eng.  matching networks. ? The materials covered in this chapter are an essential part of the 4th-year elective course ELE-863 VLSI Circuits and Systems for 

VLSI Implementation of Discrete wavelet Transform with a Fixed Booth Multiplier and Its Probabilistic Estimation
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KN Ajeesh ABSTRACT In this brief, a probabilistic estimation bias (PEB) circuit for a fixed width two's complement Booth multiplier is proposed. The proposed PEB circuit is derived from theoretical computation, Instead of exhaustive simulations and heuristic compensation 

VLSI Design of Low Power ALU Using Optimized Barrel Shifter
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ABSTRACT The purpose of this work is to design, implement and experimentally verify an Arithmetic Logic Unit (ALU) using Low Power Barrel Shifter. Barrel shifter is most widely used in ALU to perform fast shifting operations. This work evaluates the performance of 

VLSI based FFT Processor with Improvement in Computation Speed and Area Reduction
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MS Mohamed, KJ Deen, R Ganesan ABSTRACT In this paper, a modular approach is presented to develop parallel pipelined architectures for the fast Fourier transform (FFT) processor. The new pipelined FFT architecture has the advantage of underutilized hardware based on the complex 

SPURIOUS POWER SUPPRESSION TECHNIQUE FOR VLSI ARCHITECTURE
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G HEMALATHA, V VIJAYALAKSHMI ABSTRACT Using spurious power suppression technique (SPST) in VLSI will reduce the power consumption of the system significantly. Here we are going to implement this design in Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filter architecture. 

Efficient VLSI Implementation of Reduced-State Sequence Estimation for Wireless Communications
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ABSTRACT Modern wireless communication systems require efficient channel equalizer implementations. This paper explores the design space of reduced-state sequence estimation (RSSE). We show how the concept of pre-computation can be applied to 

LOW POWER BUS ENCODING FOR DEEP SUB MICRON VLSI CIRCUITS
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In recent year's low power and power aware has become a driving force in the semiconductor industry. This is due to the growth of portable electronics industry and to the growing cost of the power dissipation on buses. Because, the power dissipation related to 

An Efficient Vlsi Architecture For Removal Of Impulse Noise In Image Using Edge Preseving Filter
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ABSTRACT Images are often corrupted by impulse noise in the procedures of image acquisition and transmission. In this paper, we propose An Efficient VLSI Architecture for Removal of Impulse Noise in Image using edge preserving filter, to achieve low- 

Implementation of High-Performance Image Scaling Processor using VLSI
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ABSTRACT In this paper, a less complexity, less memory requirement, and high performance algorithm is proposed for Very Large Scale Integration implementation of an image scaling processor. The anticipated image scaling algorithm consists of a clamp filter, spatial filter 

Determination of Circuit Bi-Partition in VLSI using Ant Colony Optimization Approach
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ABSTRACT Circuit Partitioning is an important task in VLSI design and its applications. This paper discusses a new approach for Partitioning in VLSI design which is based on the Swarm Intelligence. Swarm Intelligence is a new technique of Artificial Intelligence which 

Design and Implementation of VLSI Architecture for A generalized Mixed-Radix (GMR) algorithm of FFT
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ABSTRACT Digital signal processing is one of the core technologies, in rapidly growing application Areas, such as wireless communications, audio and video processing and industrial control. The number and variety of products that include some form of digital 

A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
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G Knagge ,project.sigpromu.org ABSTRACT Multiuser detection (MUD) strategies have the poten-tial to significantly increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits that cope with real world situations and 

Modeling and Performance analysis of Metallic CNT Interconnects for VLSI Applications
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ABSTRACT THE SEMICONDUCTOR INDUSTRY is confronting an acute problem in the interconnect area as IC feature sizes continually scale below 32 nm. When the cross sectional dimension of copper wires approach their mean free path (about 40 nm at room 

Efficient VLSI Architecture for 2's Complement Based 2-D Discrete Wavelet Transform
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S Tripathi, J Jain, A Rawat ,estdl.org ABSTRACT A 2-D discrete wavelet transform hardware design based on 2's complement design based architecture is presented in this paper. We have proposed based on arithmetic for low complexity and efficient implementation of 2-D discrete wavelet transform. The 2's 

A NOVEL VLSI ARCHITECTURE OF HIGH SPEED 1D DISCRETE WAVELET TRANSFORM
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P GUPTA, SK LENKA ABSTRACT This paper describes an efficient implementation for a multi-level convolution based 1-D DWT hardware architecture for use in FPGAs. The proposed architecture combines some hardware optimization techniques to develop a novel DWT architecture that has 

VLSI Implementation of Advanced Encryption Standard using Rijndael Algorithm
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ABSTRACT Now a daysAdvanced Encryption Standard (AES) is the most efficient public key encryption system based on Rijndael Algorithm that can be used to create faster and efficient cryptographic keys. AES generates keys through the properties of the Rijndael 

VLSI Implementation of Gold Sequence by Novel Method
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ABSTRACT This paper explains the basis of the uses in CDMA technology, generation and properties of PN sequences. It shows implementation of PN and Gold sequences using 2 methods: the standard method and a modified method for improved efficiency in terms of 

A Monotonic Digitally Programmable Delay Element for Low Power VLSI Applications
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ABSTRACT Digitally programmable delay elements (DPDE) arerequired to be monotonic and low power. A lowpower digitally programmable delay element (DPDE) withmonotonic delay characteristics is proposed and a dynamiccurrent mirror together with a feedback 

Decoding For 8x8 MIMO System Using Convolution Coding Implemented In VLSI
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T Yasodha ABSTRACT The joint detection and decoding for spatial multiplexing multiple-Input multipleoutput (MIMO) system which utilize convolution Code is been proposed. The bit error rate (BER) performance of the proposed approach is significantly better than that of 

Efficient VLSI Architecture for2-D Discrete WaveletTransform by using Xilinx Simulation
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J Jain, S Shrivastava, S Sahu ABSTRACT A 2-D discrete wavelet transform hardware design based on multiplier design based architecture is presented in this paper. We have proposed based on arithmetic for low complexity and efficient implementation of 2-D discrete wavelet transform. The multiplier 

VLSI and Algorithms for High-Speed Arithmetic
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AA Liddicoat, MJ Flynn ,arith.stanford.edu ABSTRACT Area, latency, and process technology have a considerable impact on the cost- performance characteristics of floating point unit (FPU) design. Quantitative design metrics allow the FPU designer to make knowledgeable tradeoffs. Additionally, new algorithms 

On the design of 2-port SRAM memory cells using PNPN diodes for VLSI application
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X Tong, QL HaoWu, H Zhong, H Zhu, D Chen, T Ye ,in4.iue.tuwien.ac.at ABSTRACT A novel 2-port vertical PNPN diode memory cell expected to increase the SRAM integration density was proposed in this work. Its optimization design to meet the power consumption and the operational speed requirements in conventional VLSI applications 

A comparative study of Mixed CNT bundle with Copper for VLSI Interconnect at 32nm
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ABSTRACT The aggressive technology scaling in VLSI leads to decrease the size of chip. Such continual miniaturization of VLSI devices has strong impact on the VLSI technology in several ways. The performance of ICs have been increased and the interconnect delay 

Design of 64 Bit UCSLA for Low Power VLSI Application
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KJ Beryl, A Beno ABSTRACT This paper presents area and power efficient carry select adder (CSLA). This uses an uniform sized CSLA (UCSLA) with carry skip adder (CSKA) Cin= 1 instead of using Ripple Carry Adder (RCA) with Cin= 1. The delay is reduced using CSKA. The achieved 

A SUB-100-MILLIWATT DUAL-CORE HOG ACCELERATOR VLSI FOR REAL-TIME MULTIPLE OBJECT DETECTION
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K Takagi, K Mizuno, S Izumi, H Kawaguchi ,cs28.cs.kobe-u.ac.jp ABSTRACT In this paper, a Histogram of Oriented Gradients (HOG) feature extraction accelerator for real-time multiple object detection is presented. The processor employs three techniques: a VLSI-oriented HOG algorithm with early classification in Support Vector 

Estimation of Power in VLSI Circuit Using Various Simulation
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ABSTRACT With the increasing usage of electronics devices and Internet appliances, there is a corresponding increased need for employing low-power design methodologies. One of the important requirements to know during a design process is how much power the circuit 

VLSI Implementation of low Cost and high Speed convolution Based 1D Discrete Wavelet Transform
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ABSTRACT This paper presents a new VLSI architecture for a convolution based 1D discrete wavelet transform (DWT) which is intended for high speed signal and image processing. The proposed architecture employing several optimizations that enhance the 

DIGITAL VLSI ON SYSTEM CHIP DESIGN USING MULTI-HASHING TECHNIQUE
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ABSTRACT In this paper the main focus lies on increasing the security over the network using Multi-Hashing Technique. To minimize the attacks like brute force attacks, truncated hash attacks over the system or the network, the hash functions plays an eminent light 

Hardware Implementation of RC4 Stream Cipher using VLSI
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DB Rane, SR Gund, CB Pawar, JF Ukande ABSTRACT This paper deals with the design of RC4 stream cipher for wireless LAN Security. RC4 uses a variable length key from 1 to 256 bytes to initialize a 256-byte array. The array is used for subsequent generation of pseudo-random bytes and then generates a 

MODIFIED BUS INVERT TECHNIQUE FOR LOW POWER VLSI DESIGN IN DSM TECHNOLOGY
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The two main sources of power dissipation in CMOS circuits are static current, which results from resistive paths between power supply and ground, and dynamic power, which results from switching capacitive loads between different voltage levels. Reducing power 

An Analytical Report on Low Power VLSI Methods
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T Kapilachander, IH Shanavas, S Venkataraman ABSTRACT In recent days every application must need power management. In this paper we presented a various techniques to handle the power management in IC. Power dissipation in a IC is base on power used by the IC and also by heat dissipation. To 

A VLSI Architecture for Reference Frame Compression on High Definition Video Coding Systems
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G Povala, L Amaral, D Silveira, J Mattos, M Porto ,inf.ufrgs.br ABSTRACT This paper presents a hardware-friendly solution for external memory bandwidth reduction focusing in the state-ofart video encoders, like H. 264/AVC and HEVC. The proposed approach is based on reference frame compression using an adaptation of the 

Low power VLSI architecture for adaptive filter and its application to noise cancellation
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MA Shanooja, JR Kumar ,rspublication.com ABSTRACT Here we present an architectural approach to design an adaptive filter with low power consumption. The proposed architecture is efficient in achieving less power consumption without degrading the filter performance. Basically, an adaptive filter 

VLSI Design and Implementation of Ternary Logic Gates and Ternary SRAM Cell
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MNP Wanjari, MSP Hajare ,estdl.org ABSTRACT –This paper presents Very Large Scale Integration (VLSI) design and simulation of a ternary logic gates and CMOS ternary SRAM cell. The Simple Ternary Inverter, Positive Ternary Inverter and Negative Ternary Inverter are designed in 180nm technology. The 

SINGLE BIT ERROR DETECTION IN VLSI CIRCUIT
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ABSTRACT This paper examines the effect of new technology trends such as less power consumption and smaller chip feature size on very large scale integration devices. The conventional way of detecting soft error is to save one parity bit with each message word 

Experimental analysis of oxidation process of VLSI development
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MM Islam, ANMR Karim ,bjer.org ABSTRACT In this paper we extend the herculis analysis done at bostan University. This analysis works as quasi state filling algorithm with the difference of majority carrier and minimizing the error rate. This work is done by convexing maping of variables. Also it 

Analysis and Performance Comparison of CMOS and FinFET for VLSI Applications
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Complementary Metal–Oxide–Semiconductor (CMOS) has lost its credentiality during scaling beyond 32nm. Scaling causes severe Short Channel Effects (SCE) which are difficult to suppress. As a result of such SCE many alternate devices have been studied. Some of 

Voltage and Frequency Scaling in Low Power VLSI
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ABSTRACT In micro electronics design, power consumption, speed of operation, are crucial constraints. Propagation delay of circuit component has an impact on such factors. This paper investigates the effect of supply and threshold voltages and frequency at which the 

A Low-Power VLSI Technique for Digital Signal Processing Portable Electronic Devices
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ABSTRACT In portable electronic devices that operate on battery power, it is essential to have power saving techniques to increase the operating time as they are energy constrained. This paper presents a novel power saving technique supported by two design models for 

A Study on the Testing of VLSI Systems Using Reduced Power Consumption Methods
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D Hazra ABSTRACT This paper deals with the low power methods available for the testing of VLSI Systems. The problems faced have been analyzed and the solutions available are discussed. Since extra power consumption can result in severe hazards, it becomes vital 

A VLSI array processor for image and signal processing
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S Pass ,IET The GEC Rectangular Image and Data (" GRID" -see footnote) processor has the typical . It has been developed to provide a 

Modeling and Architectural Simulations of the Statistical Static Timing Analysis of the Non-Gaussian Variation Sources for VLSI Circuits
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 Static Timing Analysis of the Non-Gaussian Variation Sources for VLSI Circuits  ABSTRACT As CMOS technology scales down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. 

VLSI Implementation of 2048 Point FFT/IFFT for Mobile Wi-MAX
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UC Mehta, MS Sharma ABSTRACT This paper represents 2048 point Fast Fourier Transform and its inverse (FFT/IFFT) for Mobile Wi-MAX. Modified architecture also provides concept of local ROM module and variable length support from 128~ 2048 point for FFT/IFFT. UMC 0.18 µm is used to design 

Design and Analysis of 8-bit Low Power Parallel Prefix VLSI Adder
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SK Saptalakar, M Lakkannavar ABSTRACT The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and microprocessor data path units. As such, extensive research continues to be focused on improving the power delay performance of the adder. 

Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear
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SX Tan ,Info: ,escholarship.ucop.edu ABSTRACT This paper presents a new method of sizing the widths of the power and ground routes in integrated circuits so that the chip area required by the routes is minimized subject to electromigration and IR voltage drop constraints. The basic idea is to transform the 

AN EFFICIENT VLSI ARCHITECTURE FOR CORDIC ALGORITHM
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R PARAMESHWARAN ,iirpublications.com ABSTRACT The proposed architecture carried out makes use of n iterations to produce the final value of the function upto an accuracy of n bits. A two's complement 4-bit carry-look ahead adder/subtractor block with carry-save has been implemented as part of the 

Efficient VLSI Architectures of Split-Radix FFT using New Distributed Arithmetic
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ABSTRACT Fast Fourier transform (FFT) has become ubiquitous in many engineering applications. Efficient algorithms are being designed to improve the architecture of FFT. Among the different proposed algorithms, split-radix FFT has shown considerable 

VLSI Design and Implementation of Low Power MAC for Digital FIR Filter
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ABSTRACT In the majority of digital signal processing (DSP) applications the critical operations are the multiplication and accumulation. Multiplier-Accumulator (MAC) unit that consumes low power is always a key to achieve a high performance digital signal processing system. 

VLSI Implementation and Comparative Analysis of Memory BIST Controller using March Algorithm
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ABSTRACT With the advent of deep-submicron VLSI technology, core-based System on chip design is attracting an increasing focus. For this progress it is possible to integrate huge embedded memory core into a singe chip. However to offer a test solution for the on-chip  updated june 2013


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