multiprocessor system
Multiprocessor system for real-time convolution interpolation reconstruction
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Real-time magnetic resonance imaging (MRI) has been of increasing interest for a variety of applications that require the visualization of dynamic processes. It necessitates besides a fast acquisition method mostly an immediate reconstruction and display of the
A high speed optical common bus for a multiprocessor system
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SUMMARY One of the bottlenecks for the efficient parallel processing is the communication overheads among resources. To solve this problem, we have been developing a high speed optical communication bus, which consists of laser diodes for signal emission,
DX-Gt: Memory management and crossbar switch generator for multiprocessor system-on-a-chip
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Abstract As the number of transistors on a single chip increases rapidly, there is a productivity gap between the increasing number of available transistors and the design time. One solution to reduce this productivity gap is to increase the re usability of Intellectual The high-performance vector computers on the market are by definition (numerical) general purpose computers which hardly permit the specific properties of certain application classes to be fully exploited.(If they do so at all, then indirectly via the typical vector length and the Abstract This chapter introduces the definitions of the basic concepts used in the book. The chapter details the software and hardware organization for the heterogeneous MPSoC architectures and summarizes the main steps in programming MPSoC. The software
A programming environment for a transputer-based multiprocessor system
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Abstract This paper presents a transputer-based multiprocessor system, Hafhi 2, and the programming environment being developed for this system. Hathi 2 is mainly programmed in the language Occam, and thus the programming environment is based on the Occam
Numerical solution to the performability of a multiprocessor system with reconfiguration and rebooting delays
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ABSTRACT Multiprocessor system models are extensively used in modelling transaction processing systems, nodes in communication networks, and flexible machine shops with groups of machines. Such systems clearly, are prone to break-downs. Even if cover is
Scheduling in Multiprocessor System Using Genetic Algorithm
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Abstract Task scheduling is essential for the suitable operation of multiprocessor systems. The task scheduling is prime significance of multiprocessor parallel systems. In this paper, an efficient method based on genetic algorithms is developed to solve the multiprocessor IN RECENT YEARS, a new class of applications, requiring the transfer of digital video data, has emerged. Among the most technologically challenging are satellite-based geographical information systems that transmit high-resolution image sequences from various types of
The ACP multiprocessor system at Fermilab
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Few high energy physicists will argue with the statement that there is a severe computer cycle famine affecting several critical problems in the field. Progress is most dramatically impacted by long delays in reconstructing raw experiment event data because of the lack
Translation Lookaside Buffer Synchronization in a Multiprocessor System.
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ABSTRACT Most current computer architectures use a high- speed cache to translate user virtual addresses into physical memory addresses. On machines that require software to implement cache fills and invalidations, the software task is fairly straightforward. In a multi
The UA1 VME based data readout and multiprocessor system
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Abstract The UA1 experiment is a large multi-purpose particle physics detector system. It was designed to produce full solid-angle coverage around the LSS5 intersection region of the CERN proton-antiproton collider operating at a centre of mass of 540 Gev. The
The Hathi-2 multiprocessor system
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Hathi-2 is a recongurable general purpose multiprocessor system built of 100 Inmos T800 transputers. The system can be characterized as a loosely coupled MIMD multiprocessor, with a recongurable distributed interconnection network and a modular design. Due to its
Tango: A multiprocessor simulation and tracing system
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Abstract Tango is a software simulation and tracing system used to obtain data for evaluating parallel programs and multiprocessor systems. The system provides a simulated multiprocessor environment by multiplexing application processes onto a single processor
User adjustable process scheduling mechanism for a multiprocessor embedded system
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Abstract: The multiprocessor computer systems become more popular for the improvement of the processor's design and fabrication's evolution. In the past, the multiprocessors systems are usually adopted in server systems. Nowadays, the configurations of
A FPGA-based soft multiprocessor system for JPEG compression
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Abstract To achieve a balance between high performance and energy efficiency embedded systems often use heterogeneous multiprocessor platforms tuned for a welldefined application domain. However, due to extremely high design cost and NRE for deep
Reconfigurable Multiprocessor System Reliability Esimation
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Abstract: Reconfigurable multiprocessor systems offer an approach for improvement of system reliability. On the one hand the faults do not cause the whole system down because of the redundancy of such systems and suitable reconfiguration actions. From the other
Predictable dynamic behaviour in noc-based multiprocessor system-on-chip
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Abstract Modern streaming multimedia applications are becoming increasingly complex and dynamic. Still, designers want to give guarantees about the quality and performance of their applications. A combination of model-based design methods and predictable hardware
Conservative application-level performance analysis through simulation of a multiprocessor system on chip
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Abstract Real time applications require temporal guarantees to ensure the validity of their output. Firm RT applications must meet their temporal requirements otherwise the validity of their output sharply decreases. For these applications formal models are used to
Advanced multiprocessor system modeling
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Abstract Robust modeling is a critical ingredient for a successful multiprocessor system design methodology. This paper will present details of VHDL-based modeling developed by the Honeywell Technology Center. This modeling approach emphasizes multiprocessing
Design Rationale for Psyche a General-Purpose Multiprocessor Operating System.
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ABSTRACT The Psyche project at the University of Rochester aims to develop a high performance operating system to support a wide variety of models for parallel programming. It is predicated on the conviction that DO one model of process state or style of COlD-
Design, Analysis and Implementation of Improved Adaptive Fault Tolerant Model for Cruise Control Multiprocessor System
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ABSTRACT Safety or mission critical applications have to recover from an error within an acceptable time window or it may potentially lead to disastrous effects or higher costs. The usual industrial practice is to employ fault tolerance using hardware redundancy where
A Multiprocessor Architecture for Production System Matching.
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ABSTRACT This paper presents a new, highly parallel algorithm for OPS5 production system matching, and a multiprocessor architecture to support it. The algorithm is based on a partitioning of the Rete algorithm at the comparison level, suitable for execution on an ABSTRACT p The authors identify problems with present parallel processing systems, and present Armstrong, a hardware-software system that is designed to address some of the problems discussed. They briefly describe the Armstrong hardware and discuss, in depth, -All processors share a central bipolar memory (16MW), organized in m= 64 interleaved memory banks (four times that of CRAY-1). All banks can be accessed independently and in parallel during each machine clock period. Each processor has four parallel memory ports
A survey of multiprocessor operating system kernels (DRAFT)
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Abstract Multiprocessors have been accepted as vehicles for improved computing speeds, cost/performance, and enhanced reliability or availability. However, the added performance requirements of user programs and functional capabilities of parallel hardware introduce
A multiprocessor DSP system for a high throughput control application
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Abstract This paper describes the hardware concept and realization of an experimental multiprocessor system with Digital Signal Processors TMS320C6701. For convenience and efficiency piggyback modules have been used. The structure is organized in master-slave
Implementation issues for the Psyche multiprocessor operating system
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ABSTRACT: Psyche is a parallel operating system under development at the University of Rochester. The Psyche user interface is designed to allow programs with widely differing concepts of process, sharing, protection, and communication to run efficiently on the same
A VME multiprocessor architecture for the LEP/SPS control system
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Abstract The control system for the LEP collider follows the concepts developed for the SPS accelerator but making use of present-day technology. Conventional minicomputers are replaced by Process-Control Assemblies constructed in the VME standard using the
Performance estimation for a dynamically reconfigurable multiprocessor system applied to low-level image processing
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Abstract: This paper describes lhe performance testing of a parallel, fixed-valency processor system, which is primarily intended for low-level image processing, though the techniques developed have wide applicability. By tweaking ihe hardware of a Parsys Supernode it
A Processor Queuing Simulation Model for Multiprocessor System Performance Analysis
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Abstract This paper describes a processor queueing simulation model for a complex processor that aggressively issues instructions with the use of outof-order, multiple issue and multithreading. The model is developed for memory and system evaluation of memory
Real-time Processor Interconnection Network for FPGA-based Multiprocessor System-on-Chip (MPSoC)
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Abstract:This paper introduces a new approach for a network on chip (NOC) design which is based on a NlogN interconnect topology. The intended application area for the NOC is the real-time communication of multiprocessors that are hosted by a single Field
LFS--A Local File System for Multiprocessor NFS Network Servers
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ABSTRACT This report discusses the design and implementation of a special-purpose Unix file system interface, called LFS, that lies at the heart of a new multiprocessor NFS file server. This server addresses the latest generation of RISC-based Unix workstations, The primary goal of system-level modelling is to formulate a model within which a broad class of designs can be developed and explored. Ultimately, this allows designers to efficiently implement instances of systems within a single modelling style as supported by
Real-Time Operating System design for Multiprocessor system-on-a-chip
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Summary The primary goal for real-time kernel software for single and multiple-processor on a chip is to support the design of timely and cost-effective systems. The kernel must provide time guarantees, in order to predict the timely behavior of the application, an extremely
Analysis of a Dynamic Load Balancing in Multiprocessor System
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ABSTRACT Dynamic load balancing is an important factor affecting the parallel computing performance in a multiprocessor system. On the basis of an introduction to the principle of dynamic load balancing algorithm, we will find the rated efficiency, throughput, speedup,
A multiprocessor extension to the conventional file system interface
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Abstract As the I/O needs of parallel scienti c applications increase, le systems for multiprocessors are being designed to provide applications with parallel access to multiple disks. Many parallel le systems present applications with a conventional Unix-like The scheduling problem Scheduling applications in computer science range from HL-Synthesis through Real-Time Embedded Systems to HW/SW-Co-design. We deal with a STATIC scheduling pro- blem for a heterogeneous multiprocessor system, where TASKS have to be assigned
Load Balancing in the Macro Pipeline Multiprocessor System using Processing Elements Stealing Technique
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ABSTRACT The exponential increase in amount of processing power required by applications has been observed to be disproportionately leading the available processing power. Recent researches have shown that the key to balance this disproportionate is to
Preliminary basic performance analysis of the cedar multiprocessor memory system
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Abstract In this paper we present some preliminary basic results on the performance of the Cedar multiprocessor memory system. Empirical results are presented and used to calibrate
A performance study of workfile disk management for concurrent mergesorts in amultiprocessor database system
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Abstract This paper studies the impacts of workfile disk allocation and data striping on the performance of concurrent mergesorts in a multiprocessor database system. We examine through detailed simulations an approach where workfile disks are logically partitioned
A Multistep Approach for Restructuring and Mapping Distributed Object-Oriented Software onto a Multiprocessor System
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Abstract A large number of Distributed Object Oriented (DOO) systems have been developed for solving complex problems in various scientific fields. In a distributed object- oriented application, classes can run on a separate computer within a network system. So,
Approximate analysis of common memory access contention in a multiprocessor controlled switching system
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ABSTRACT This paper presents a queueing network model for common memory access contention and access contention to common data that cannot be referenced by more than one processor in a multiprocessor controlled switching system. The model takes into The recent development of multiprocessor computer systems permits one to carry out numerical simulation of complicated physical phenomena, including hydrodynamic flows, in the 3D statement. Special algorithms are required to use many processors effectively.
Task scheduling and memory partitioning for multiprocessor system-on-chip using low-power L2 cache architecture
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ABSTRACT Significant portion of cache energy in a highly associative cache is consumed during tag comparison. In this paper tag comparison is carried out by predicting both cache hit and cache miss using multistep tag comparison method. A partially tagged bloom filter
DRM system-a distributed real-time multiprocessor system
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Because of the growing interest in distributed computer architectures the Philips Research Labs began, in the early 1970's, a research project on the hardware and software aspects of distributed systems. As one of the results of this project a prototype system, called
Operating System for a Real-Time Multiprocessor Propulsion System Simulator
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ABSTRACT The NASA Lewis Research Center is developing and evaluating experimental hardware and software systems to help meet future needs for real-time, high-fidelity simulations of air-breathing propulsion systems. Specifically, the Real-Time
Case Study in Prototyping with Rapide: Shared Memory Multiprocessor System
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Abstract Rapide is a concurrent object-oriented language designed for prototyping distributed systems. This paper describes the creation of such a prototype, more speci cally a shared memory multiprocessor system. The design is presented in an evolutionary
The FLASH Multiprocessor: designing a flexible and scalable system
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Abstract The choice of a communication paradigm, or protocol, is central to the design of a largescale multiprocessor system. Unlike traditional multiprocessors, the FLASH machine uses a programmable node controller, called MAGIC, to implement all protocol processing
A Multiprocessor System for Real-Time Robotic Applications
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Abstract: The paper deals with the design and implementation of a multiprocessor, MRTA, having multiple module architecture. Each module consists of a tightly coupled set of processors connected to a shared resource by means of a multiport bus. A shared ABSTRACT System-level low power scheduling techniques are required for optimizing th performance and power of embedded applications that are mapped to multiprocessor System-on-Chip (SoC) architectures. In this paper, we present an integer linear
A multiprocessor system with multitasking facilities
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The starting point of the work reported in this thesis was a study of the possibilities of increasing the performance of a computer system by structural means. This is an alternative to increasing the performance by using faster basic circuitry in a conventional structure.
Checking the integrity of memory in a snooping-based symmetric multiprocessor (smp)system
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Abstract We study schemes to implement memory integrity checking in a symmetric multiprocessor (SMP) system. We focus on a snooping-based SMP system, where the processors are connected by a single bus. The problem has two parts, checking the
Heterogeneous Multiprocessor System Design with ESPAM: Integration of Hardware IP Cores
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Embedded systems nowadays need to support ever-increasing functionality and high flexibility, which calls for the emergence of multiprocessor systems, in place of single processor systems, for the embedded System-on-Chip platforms. The multiprocessor
Design and implementation of a multiprocessor system for position and attitude control of an underwater robotic vehicle
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ABSTRACT The Multimode Proximity Operations Device (MPOD) is a neutral buoyancy simulation telerobot with the capability to fly in three dimensions and dock with an underwater satellite mockup. The vehicle may be flown from onboard, underwater remote,
A methodology for efficient multiprocessor system-on-chip software development.
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1.1 Background Our lifestyles have been greatly changed by the various new electronic devices, which continuously appear in today's market. For example, Personal Navigation Assistants (PNAs) help people to find driving direction without the need to read a map;
Efficient system-level fault diagnosis of large multiprocessor systems
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This document presents new results in different areas of multiprocessor fault tolerance. The first main topic of research studied is fault diagnosis of large parallel computers. Both the centralized and distributed approach to fault diagnosis are considered. In the framework of
Evaluation of Application-Specific Multiprocessor Mobile System
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ABSTRACT The popularity of application-specific computing systems is on the rise and many systems have been developed in fields such as multimedia, high-speed networks, information systems, signal and image processing. Real-time application-specific systems
Managing the overall balance of operating system threads on a multiprocessor using automatic self-allocating threads (ASAT)
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While commodity processor based parallel processing systems have an advantage over traditional supercomputers in price/performance, traditional supercomputers retain a significant advantage over parallel processing systems in the area of flexibility. Traditional
Asymptotic Analysis of Phase Control System for Clocks in Multiprocessor Arrays.
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Abstract: New method for the rigorous mathematical analysis of electronic synchronization systems is suggested. This method allows to calculate the characteristics of phase detectors and carry out a rigorous mathematical analysis of transient process and stability of the
Chip Multiprocessor Platform for Ultra-Low-Power Data-Driven Networking System: ULP-DDNS
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Abstract:An ultra-low-power networking protocol handling platform is urgently required to realize sustainable ad hoc communication over battery-operated devices in emergent situations without connectivity to the wired network infrastructure. In this paper, the data-
Optimizing Communication Bottlenecks in Multiprocessor Operating System Kernels
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Abstract One difficulty of programming multicore processors is achieving performance that scales with the number of cores in the system. A common performance optimization is to increase inter-core parallelism. If the application is sufficiently parallelized, developers
A multiprocessor tree-searching system design
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Abstract Sequential versions of the alpha-beta search algorithm have been improved by refinements such as iterative deepening, narrow window searching and the use of memory tables. The design issues affecting a parallel implementation are discussed with emphasis
The fast Amsterdam multiprocessor (FAMP) system hardware
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Abstract The architecture of a multiprocessor system is described that will be used for online filter and second stage trigger applications. The system is based on the MC68000 microprocessor from Motorola. Emphasis is paid to hardware aspects, in particular the
Using operating system instrumentation and event logging to support user-levelmultiprocessor schedulers
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Abstract This work presents a novel approach to support multiprocessor scheduling at userlevel. We propose to use system instrumentation and event logging to obtain runtime information relevant for scheduling, from different system sources such as the hardware,
Design and Benchmarking of Real-Time Multiprocessor Operating System Kernels
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ABSTRACT Multiprocessor architectures, operating systems and real-time technologies are all interesting and highly advanced topics. Real-time demands inject an additional correctness criterion into computer systems. It is not just the result that is important, timing The laboratory described below was designed with three major goals in mind: (1) relatively easy use by experimenters with only minimal computer experience, (2) maximum flexibility in terms of the type of visual displays that can be generated and subject responses that can be
Hardware Implementation of an Improved Resource Management Scheme for Fault Tolerant Scheduling of a Multiprocessor System
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ABSTRACT Safety-critical systems have to be fault tolerant and also meet stringent temporal constraints. Various redundancy strategies are built into such mission-critical applications to ensure the overall success of the mission. This paper implements a fault tolerant
System-level model for a GALS massively parallel multiprocessor
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(Spiking neural network architecture) computing system is characterized by its tremendous computation and communication power. We adopted a globally asynchronous locally synchronous (GALS) approach to interconnect a large
Electrical Design of an MCM for a Multiprocessor System
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ABSTRACT This paper details the electrical design of a multichip module (MCM) which represents a single node ol a multiprocessor digital system. After a brief overview on the architecture, the paper discusses the key performance related ingredients of the MCM
Application of the FAMP multiprocessor system in experiment NA11 at the SPS
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Abstract A second level trigger system is discussed, which will be implemented in the experiment NA11 at the CERN-SPS. The experiment studies hadron interactions with a two magnet single-arm spectrometer. The second level trigger will select events depending on
The Design and Implementation of Multiprocessor Support for an Industrial OperatingSystem Kernel.
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Abstract The ongoing transition from uniprocessor to multi-core computers requires support from the operating system kernel. Although many general-purpose multiprocessor operating systems exist, there is a large number of specialized operating systems which require
3D-TV Rendering on a Multiprocessor System on a Chip
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In this paper we describe how two 3D-TV rendering algorithms have been mapped onto a chip multiprocessor named Wasabi. This platform contains several TriMedia processors that communicate via a shared memory, fast message-passing channels to
Analysis of the Fault-Free Behavior of the FTMP Multiprocessor System: Baseline Measurements and Synthetic Workload Development Master Project
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Abstract 1. Introduction 2. Background 2.1 Proposed Methodology 2.2 Overview of Experiment Environments 2.2. 1 Stage 1-Standalone 2.2. 2 Stage 2-Operating System (OS) 2.2. 3 Stage 3-Integrated Instrumentation Environment 2.3 Present and Future Experiment
The design of a distributed kernel for a multiprocessor system
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Page 1. The Design of a Distributed Kernel for a MultiprocessorSystem by PATRICK DAVID BOYLEprovides the same environment uniformly and transparently throughout the multiprocessor system. Distributed Verex has been implemented and is undergoing continuing
The Topaz system: Distributed multiprocessor personal computing
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The Topaz distributed operating system, which runs on the Firefly multiprocessor, was built at Digital's Systems Research Center (SRC) in order to support current computing needs and to provide a basis for research into distributed personal computing. In this paper, we
Designing multiprocessor scheduling algorithms using a distributed genetic algorithmsystem
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Abstract Processor scheduling algorithms for parallel computing systems are often designed using analytical modeling, simulations, and/or trialand-error experiments. These approaches are usually quite timeconsuming and produce only satisfactory solutions. To automate this
FPGA Implementation of a Time Predictable Memory Controller for a Chip-Multiprocessor System
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Abstract (English) The use of modern conventional architectures in real-time systems (RTS) requires complex analysis and suffers from high resource over-allocation needed to cover uncertainties stemming from employed speculative, average case optimizations. The
Research on a system performance with parallel modes of execution in a multiprocessorcomputer system with hyper-threading technology
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Abstract: This paper represents a research into the new Hyper-Threading Technology (TH) being introduced with the Intel Xeon family processors. Many applications expect maximum efficient exploitation of the hardware capability in the computer configuration. That
Performance and Implementation Complexity in Multiprocessor Operating System Kernels
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Abstract The increasing use of multiprocessor computers require operating system adaptations to take advantage of the computing power. However, porting an operating system kernel to run on a multiprocessor can be very difficult because of a large code
Evaluation of on-chip multiprocessor architectures for an embedded cartographic system
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ABSTRACT Embedded systems with complex graphical interfaces require significant computational power. Moreover, low power consumption and low cost are usually strict specification constraints. A possible solution for addressing these conflicting needs is the
SDCC-RTP and RTPGen: A C-to-FPGA system-on-programmable-chip system generator for multiprocessor embedded systems
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Abstract Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young University leverages the advances in FPGA technology with a system architecture that is
THE DEVELOPMENT OF ASYNCHRONOUS MULTIPROCESSOR CONCFPTS FOR FLIGHT CONTROL SYSTEM APPLICATIONS
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As aircraft designers have striven for more and more aerodynamic performance, the aircraft's natural stability and control characteristics have deteriorated. This has required the application of increasingly complex feedback control systems in order to artificially restore
An embedded, generic and multiprocessor hardware operating system
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Abstract This paper presents a hardware real time operating system (HW-RTOS) for multiprocessors. A Virtual Platform (SystemC) and Prototyping Platform (FPGA board) have been designed to be generic, modular and to support multiprocessor architectures and the
A PC104 multiprocessor dsp system for radiation spectroscopy applications
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Abstract A multiprocessor DSP system hosted in a PC104 Windows CE industrial PC is presented. It is based on a master floating point Digital Signal Processor (DSP), a scalable number of slave DSPs and, special purpose trigger, pulse locator and data routing digital
The clustered multikernel: An approach to formal verification of multiprocessor operating-system kernels
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Abstract The key software component of a computer system is the operating-system kernel. It always needs to be trusted because it runs in the CPU's privileged mode and therefore has access to all system components. Consequently, kernel correctness is crucial for secure,
Development of an MM5-based Four-Dimensional Variational Analysis System for Distributed Memory Multiprocessor Computers
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The Air Force Research Laboratory is leading a multi-year effort to develop an updated version of the National Center for Atmospheric Research/Penn State University Fifth Generation Mesoscale Model (MM5) four-dimensional variational analysis (4DVAR)
Multiprocessor implementation of a face detection system
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Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas; including banking and security system access control, video surveillance, and multimedia
Simulating multiprocessor database system architectures
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Abstract In this paper we propose a new approach to simulating parallel hardware architectures based on the hierarchical database system model, and an architecture simulator is implemented based on this new approach. This simulator allows for the
Embedded System-level Platform Synthesis and Application Mapping for Heterogeneous and Hierarchical Multiprocessor Systems
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Nowadays, modern embedded applications are becoming complex. Such complex embedded applications lead to a single processor embedded system architecture can no longer meet the performance requirements of these applications. Therefore, in order to
Centralized Multiprocessor Control System for the Frascati Storage Rings DAONE
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Abstract We describe the status of the DANTE ( New Tools Environment) control system for the new DA J NE -factory under construction at the Frascati National Laboratories. The system is based on a centralized communication architecture for
Implementation issues and evolution of a multiprocessor operating system port
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Abstract. As multiprocessors become more and more common, operating system support for these systems is increasingly important. In this paper, we describe the evolution and performance of a multiprocessor port of a special-purpose cluster operating system. The
Lessons Learned During the Development of the CapoOne Deterministic MultiprocessorReplay System
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Page 1. Lessons Learned During the Development of the CapoOne Deterministic Multiprocessor Replay System Department of Computer Science University of Illinois at Urbana-Champaign
BUS BASED MULTIPROCESSOR SYSTEM FOR WIND SPEED REGISTRATION
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Wind speed and wind direction are the most important parameters used in the wind measurements. Their values are measured in different ways but the most commonly used device for it is the rotational anemometer. In the paper a bus based multiprocessor system
A Module Scheduling for Multiprocessor System Based on Memetic Algorithms
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Abstract:-In multiprocessor systems, an efficient scheduling of a parallel program onto the processors that minimizes the entire execution time is vital for achieving a high performance. The problem of multiprocessor scheduling can be stated as finding a schedule for a
A Programming Environment for a Transputer-Based Multiprocessor System
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Abstract This paper presents a transputer-based multiprocessor system, Hathi -2, and the programing environment being developed for this system. Hathi-2 is mainly programmed in the language Occam, and thus the programming environment is based on the Oceans
A Real-time Software Broadband Beamformer on the IBM Cyclops Multiprocessor System
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Abstract. Digitally beamforming broadband signals of several hundred MHz of bandwidth in real time, is computationally highly expensive and very demanding. Performing this task in software is even more challenging. However, with the emergence of massively parallel
Application of the Co-design Finite State Machines Model for the Design of a Multiprocessor System
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Abstract:-This paper presents the use of CFSMs, Co-design Finite State Machines, for the high level design of multiprocessor system. This technique is based on implementationindependant representation that can be generated from a variety of
Optimization Techniques for Task Scheduling in Multiprocessor System-A Review
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Abstract:The multiprocessor scheduling can be defined as scheduling a task graph in a way such that performance criteria is optimized. Optimization is a mechanism of finding minimum and maximum values from a given set of values. This is done by taking some
Self-adaptive multiprocessor system approach
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the place at which the family will be
Hierarchical QoS Concept for Multiprocessor System-on-chip
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Resource-constrained systems require that Quality of Service (QoS) is an integral part of the system design. In this paper, we provide a new QoS concept to be used in a large Network- on-Chip (NoC) setup for complex multimedia applications. The trend in video consumer
Traffic Pattern Analysis in Multiprocessor System
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Abstract It is very important to manage resources in multiprocessor system used in real time systems so that deadline violation is minimized. Fluid traffic flow conditions results in disruptive scheduling. In this paper we enumerate the why's and how's of disruptions in
Integrating cache space reservations with processing cycles reservations for amultiprocessor system on chip
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Abstract This article presents the initial steps towards integrating a cache space reservation mechanism with processing cycles reservations. Consumer electronics vendors increasingly deploy shared-memory multiprocessor SoCs, to balance flexibility (late changes, software
Multiprocessor System-on-Chip Data Memory Customization for Embedded Array-Intensive Applications
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The memory subsystem is one of the important contributors to embedded system power consumption, which in turn is one of the limiting resources in mobile systems. As explained in Chapter 1, a number of methods have been proposed to reduce memory power
Advancing Software Development for a Multiprocessor System-on-Chip
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ABSTRACT A low-level language is the right tool to develop applications for some embedded systems. Notwithstanding, a high-level language provides a proper environment to develop the programming tools.target device is a system-onchip consisting of an
Hybrid method for solving incomplete linear optimization problem on distributed memorymultiprocessor system
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Abstract An approach to solving the linear optimization problem with unformalized restrictions is proposed. This approach is oriented to distributed memory multiprocessor systems. A parallel algorithm, based on combination of linear programming and
A Comparative Study on Dynamic Scheduling of Real-Time Tasks in Multiprocessor System using Genetic Algorithms
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ABSTRACT Multiprocessors have evolved as powerful computing tools for executing dynamic real time tasks. The continual evolutions of the multiprocessor and real-time systems in the last few decades have encouraged the research and development of a new
PIPELINED ON-LINE BACK-PROPAGATION TRAINING OF AN ARTIFICIAL NEURAL NETWORK ON A PARALLEL MULTIPROCESSOR SYSTEM
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Abstract:This work presents an on-chip learning of artificial neural networks in a FPGA multiprocessor system, where each neuron is implemented in a soft-core processor. In order to take maximum advantage of the distributed architecture, a pipelined version of the on- It is possible to divide all computers~ existing at present time, into two large classes. The first class includes the general-purpose computers and the second class special-purpose computers. Each class of the computers has its own advantages and defects. The general-
Enhancing the Price/Performance of a Clustered Multiprocessor System
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Abstract In this paper, we will explore the design considerations of a low cost, high performance microprocessor cluster, including both hardware and software factors. The goal of the designed system is to maximize the ratio of performance to price, creating a
Sorting Algorithms implemented over a Hypercube Multiprocessor System
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Abstract: The problems of sorting large data arrays into a multiprocessor system are discussed. A basic multiprocessor architecture is an n-dimensional hypercube. Only one of the processors in the hypercube is connected with an external user/host processor/.
Low Latency on Chip Permutation Network for Multiprocessor System On-Chip
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Abstract: This On-Chip Permutation Network for Multiprocessor System-On-Chip presents the silicon-proven design of a novel on-chip network to support guaranteed traffic permutation in multiprocessor system-on-chip applications the routing algorithm, the
PARNEU: Scalable Multiprocessor System for Soft Computing Applications
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Abstract:-Many soft computing applications have inherent parallelism in the form of synapses and neurons. Exploitation of parallelism will bring computers more close to their biological counterparts as well as improve the performance. Modularity and good
DESIGN OF A SELF-ADAPTIVE ON-CHIP PERMUTATION NETWORK FOR MULTIPROCESSOR SYSTEM-ON-CHIP
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ABSTRACT This paper presents the silicon-proven design of a novel on-chip network to support guaranteed traffic permutation along with a selfcontained adaptive system for detecting and bypassing permanent errors in multiprocessor system-on-chip applications.
Design and Performance Analysis of Reconfigurable Hybridized Macro PipelineMultiprocessor System (HMPM)
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ABSTRACT Multiprocessor systems' speed and throughput has surpassed the superscalar uniprocessor, making the attentions drawn towards new ways of increasing the efficiency and speed of the multiprocessor. Software developmental approaches are now being
A Heterogeneous Multiprocessor System-on-Chip Architecture Incorporating Memory Allocation
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Abstract This paper describes the development of a Multiprocessor System-on-Chip (MPSoC) with a novel interconnect architecture incorporating memory allocation. It addresses the problem of mapping a process network with data dependent behavior and
Multiprocessor System Emulator For Digital Devices Modeling
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Abstract: A program model (the emulator) of specialized multiprocessor computer for synthesized digital devices simulation is described in the paper. Functioning of the multiprocessor computer and its software model is based on the solution of Boolean
The parallel image processing on the TMS320C80 multiprocessor system
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The digital image processing and recognition requires great computation power. Thus in many applications connected with that field some specialised processors or FPGA structures must be used. An alternative approach proposed by The Texas Instruments is a single- In this system, there are seven processors: one master, one communication processor, one diagnostic processor, and four slaves. For each processor, the computation phase is divided into two phases: autonomous phase and communication phase. During the We created pipelined MPSoCs for the multimedia applications of Figure 1 using a commercial design environment from Tensilica We used Xtensa LX2 processor that provides an Application Specific Instruction set Processor (ASIP) platform for creation of
Modeling and Performance Evaluation of Multiprocessor System Using General Stochastic Petri net
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Abstract:Petri Nets are used in the field of computer science for modeling system performance. In this paper, Generalized Stochastic Petri Net (GSPN) is used to model multiprocessor parallel processing architectures. This paper by means of Generalized
A Knapsack Scheduling Algorithm for Soft Real-time Multiprocessor System
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Abstract:Due to the development of commercial multicore architectures, scheduling in Multiprocessor real-time system has attracted huge research interests and various algorithms have been proposed. However, most prior research on real-time scheduling on
A LOOSELY COUPLED MULTIPROCESSOR SYSTEM: ADMS
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Abstract We have described on the basic design of ADMS,'already IAma86 i. ln this paper, we add some results o our works concerning with the logigal configuration and, ghe operating system of ADMS to the previous report ·The reasons of use of the capability-
An Implementation of a Cache Coherence Protocol on an ATM-Based Multiprocessor System
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Abstract Intersystem and intrasystem networks have long existed separately, each with their own unique characteristics. Intersystem communication tends to emphasize high network uti- lization while intrasystem networks focus on reducing latency. However, the development
Dynamic Resource Allocation in a Hierarchical Multiprocessor System: A Preliminary Study
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Abstract In this report, an integrated system approach to dynamic resource allocation is proposed. Some of the problems in dynamic resource allocation and the relationship of these problems to system structures are examined. A general dynamic resource allocation
Fuzzy Scheduling Algorithm for Real Time multiprocessor system
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Abstract: In a multiprocessor environment scheduling is very essentially done with greater challenges. Researchers are in the edge of finding solutions to these challenges. Scheduling is the art of allocating limited resources to competing tasks over time. A
MULTIPROCESSOR SYSTEM-ON-CHIP IMPLEMENTATION FOR NETWORK-ON-CHIP COMMUNICATION WITH 5-BIT DATA LINE
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ABSTRACT This paper introduces the silicon-proven method of different On-Chip interconnection networks or Network-on-Chips (NoCs). These Network-on-Chips (NoCs) are becoming the de-facto scaling communication techniques in Multi-Processor System-on-
Performance evaluation of Grace Hash-Join algorithm on the KSR-1 multiprocessor system
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I am extremely grateful to Dr. Andrew Francis Laine and Dr. Herman Lam for agreeing to serve on my committee and for their careful perusal of this thesis. Thanks also go to Dr. Haruo Yokota at Japan Advanced Institute of Science and Technology for his insightful
Hathi-2 multiprocessor system
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Hathi-2 is a reconfigurable general-purpose looselycoupled MlMD multiprocessor system consisting of 100 32-bit lMS T800 transputers and 25 76-bit lMS T212 transputers. Hathi-2 has a distributed switching network and a distributed control system which contains an
Low-Power L2 Cache Architecture for Multiprocessor System on Chip Design
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Abstract:Significant portion of cache energy in a highly associative cache is consumed during tag comparison. In this paper tag comparison is carried out by predicting both cache hit and cache miss using multistep tag comparison method. A partially tagged bloom filter
Self-Tuned Distributed Multiprocessor System
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Abstract. Self-tuning, a technique devised by Ted Kehl, is a new clocking paradigm which incorporates the best features of conventional synchronous logic along with advantages offered by the asynchronous, self-timed paradigm. The principles of self-tuning are
A Modular Expandable Multiprocessor System with Fault Tolerance
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Abstract The experimental multiprocessor system MEMSY 2 will be described. This system was built to validate the concept of the MEMSY architecture-a scalable multiprocessor architecture based on local shared-memory. Main application areas are scientific
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